Crystal Oscillator. Si565 Datasheet

Si565 Oscillator. Datasheet pdf. Equivalent

Part Si565
Description Crystal Oscillator
Feature Ultra Series™ Crystal Oscillator (VCXO) Si565 Data Sheet Ultra Low Jitter Any-Frequency VCXO (100 f.
Manufacture Silicon Laboratories
Datasheet
Download Si565 Datasheet



Si565
Ultra SeriesCrystal Oscillator (VCXO)
Si565 Data Sheet
Ultra Low Jitter Any-Frequency VCXO (100 fs), 0.2 to 3000
MHz
The Si565 Ultra Seriesvoltage-controlled crystal oscillator utilizes Silicon Labo-
ratories’ advanced 4th generation DSPLL® technology to provide an ultra-low jit-
ter, low phase noise clock at any output frequency. The device is factory-pro-
grammed to any frequency from 0.2 to 3000 MHz with <1 ppb resolution and
maintains exceptionally low jitter for both integer and fractional frequencies
across its operating range. On-chip power supply filtering provides industry-lead-
ing power supply noise rejection, simplifying the task of generating low jitter
clocks in noisy systems that use switched-mode power supplies. Offered in in-
dustry-standard 3.2x5 mm and 5x7 mm footprints, the Si565 has a dramatically
simplified supply chain that enables Silicon Labs to ship custom frequency sam-
ples 1-2 weeks after receipt of order. Unlike a traditional XO, where a different
crystal is required for each output frequency, the Si565 uses one simple crystal
and a DSPLL IC-based approach to provide the desired output frequency. The
Si565 is factory-configurable for a wide variety of user specifications, including
frequency, output format, and OE pin location/polarity. Specific configurations are
factory-programmed at time of shipment, eliminating the long lead times associ-
ated with custom oscillators.
Pin Assignments
VC 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
KEY FEATURES
• Available with any frequency from 200 kHz to
3000 MHz
• Ultra low jitter: 100 fs RMS typical
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise immunity:
–80 dBc Typ
• 3.3 V, 2.5 V and 1.8 V VDD supply operation
from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/25G/40G/100G Ethernet
• 56G/112G PAM4 clocking
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, NICs, search
acceleration
• Test and measurement
• FPGA/ASIC clocking
Pin #
1
2
3
4
5
6
(Top View)
Descriptions
VC = Voltage Control Pin
OE = Output enable
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
OSC
Digital
Phase
Detector
Phase Error
Cancellation
Digital
Loop
Filter
Phase Error
DCO
Vc ADC
Fractional
Divider
Control
NVM
Power Supply Regulation
Output Enable
(Pin Control)
Built-in Power Supply
Noise Rejection
Low
Noise
Driver
Flexible
Formats,
1.8V – 3.3V
Operation
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Si565
Si565 Data Sheet
Ordering Guide
1. Ordering Guide
The Si565 VCXO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access
this tool and for further ordering instructions.
VCXO Series
Description
565 Single Frequency VCXO
Code
A
B
OE Pin
Pin 2
Pin 2
OE Polarity
Active High
Active Low
Package
A 5x7 mm
B 3.2x5 mm
Temperature Grade
G -40 to 85 °C
565 A A A - - - - - - - A B G R
Signal Format
LVPECL
LVDS
CMOS
CML
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
(Complementary)
Custom1
VDD Range
2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
Order
Option
A
B
C
D
E
F
G
X
Temperature Stability = ± 20 ppm
Vc Tuning
Slope
Kv [ppm/V]
Min APR [± ppm] at VDD 3
3.3V 2.5V 1.8V
A 60
20 --
--
B 75
40 20
--
C 105
70 40 20
D 150
115 75
45
E 180
145 100
65
F 225
190 135
85
Device Revision
Code
R
<Blank>
Reel
Tape and Reel
Coil Tape
Frequency
Code 2
Mxxxxxx
xMxxxxx
xxMxxxx
xxxMxxx
xxxxMxx
xxxxxx
Description
FCLK < 1 MHz
1 MHz FCLK < 10 MHz
10 MHz FCLK < 100 MHz
100 MHz FCLK < 1000 MHz
1000 MHz FCLK < 3000 MHz
Custom code if FCLK > 6 digits
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Create custom part numbers at www.silabs.com/oscillators.
3. Min Absolute Pull Range (APR) includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
a. For best jitter and phase noise performance, always choose the smallest Kv that meets the application’s minimum APR re-
quirements. Unlike SAW-based solutions which require higher Kv values to account for their higher temperature dependence,
the Si56x series provides lower Kv options to minimize noise coupling and jitter in real-world PLL designs.
b. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an APR of ±20 ppm is able to lock to a
clock with a ±20 ppm stability over 20 years over all operating conditions.
c. APR (±) = (0.5 x VDD x tuning slope) - (initial accuracy + temp stability + load pulling + VDD variation + aging).
d. Minimum APR values noted above include absolute worst case values for all parameters.
e. See application note, "AN266: VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR)" for more information.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
Development Kits
www.silabs.com/Si565-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
www.silabs.com/oscillator-tools
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