DIGITAL ISOLATOR. Si8460 Datasheet

Si8460 ISOLATOR. Datasheet pdf. Equivalent

Part Si8460
Description LOW POWER SIX-CHANNEL DIGITAL ISOLATOR
Feature Si8460/61/62/63 LOW POWER SIX-CHANNEL DIGITAL ISOLATOR forNotNeRwecDoesmigmnesnded Features  Hi.
Manufacture Silicon Laboratories
Datasheet
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Si8460
Si8460/61/62/63
LOW POWER SIX-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
Up to 2500 VRMS isolation
DC to 150 Mbps
60-year life at rated working
No start-up initialization required voltage
Wide Operating Supply Voltage: Precise timing (typical)
2.70–5.5 V
<10 ns worst case
Wide Operating Supply Voltage: 1.5 ns pulse width distortion
2.70–5.5V
0.5 ns channel-channel skew
Ultra low power (typical)
2 ns propagation delay skew
5 V Operation:
6 ns minimum pulse width
< 1.6 mA per channel at 1 Mbps Transient Immunity 25 kV/µs
< 6 mA per channel at 100 Mbps Wide temperature range
2.70 V Operation:
–40 to 125 °C at 150 Mbps
< 1.4 mA per channel at 1 Mbps RoHS-compliant packages
< 4 mA per channel at 100 Mbps SOIC-16 narrow body
High electromagnetic immunity
Applications
Industrial automation systems
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communications systems
Safety Regulatory Approvals
UL 1577 recognized
Up to 2500 VRMS for 1 minute
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in a 16-pin narrow-
body SOIC package.
Ordering Information:
See page 28.
Rev. 1.6 4/18
Copyright © 2018 by Silicon Laboratories
Si8460/61/62/63



Si8460
TABLE OF CONTENTS
Si8460/61/62/63
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . . 26
3.2. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.6
2





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