M15F2G16128A-DEBIG2B

ESMT DDR3 SDRAM Feature z Interface and Power Supply „ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) z JEDEC DDR3 Compliant „ 8n Prefetch Architecture „ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) „ Double-data rate on DQs, DQS and DM z Data Integrity „ Auto Self Refresh (ASR) by DRAM built-in TS „ Auto Refresh and Self Refresh Modes z Power Saving Mode „ Power Down Mode z Signal Integrity „ Configurable DS for system compatibility „ Configurable On-Die Termination „ ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) M15F2G16128A (2B) Operation Temperature Condition -40°C~95°C  16M x 16 Bit x 8 Banks DDR3 SDRAM z Signal Synchronization 1 „ Write Leveling via MR settings „ Read Leveling via MPR z Programmable Functions „ CAS Latency (5/6/7/8/9/10/11/13) „ CAS Write Latency (5/6/7/8/9) „ Additive Latency (0/CL-1/CL-2) „ Write Recovery Time (5/6/7/8/10/12/14/16) „ Burst Type (Sequential/Interleaved) „ Burst Length (BL8/BC4/BC4 or 8 on ...