DatasheetsPDF.com

M15F2G16128A-DEBG2LS Dataheets PDF



Part Number M15F2G16128A-DEBG2LS
Manufacturers ESMT
Logo ESMT
Description 16M x 16 Bit x 8 Banks DDR3 SDRAM
Datasheet M15F2G16128A-DEBG2LS DatasheetM15F2G16128A-DEBG2LS Datasheet (PDF)

ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM  Data Integrity ˗ Auto Self Refresh (ASR) by DRAM built-in TS ˗ Auto Refresh and Self Refresh Modes  Power Saving Mode ˗ Power Down Mode  Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT im.

  M15F2G16128A-DEBG2LS   M15F2G16128A-DEBG2LS


M15F2G16128A-EFBG2LS M15F2G16128A-DEBG2LS AH3502


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)