/ Demultiplexer. 54HC138 Datasheet

54HC138 Demultiplexer. Datasheet pdf. Equivalent

Part 54HC138
Description 3-Line to 8-Line Decoder / Demultiplexer
Feature High Speed CMOS Logic – 54HC138 3-Line to 8-Line Decoder / Demultiplexer in bare die form Rev 1.0 .
Manufacture Silicon Supplies
Datasheet
Download 54HC138 Datasheet

54HC138 Datasheet
High Speed CMOS Logic – 54HC138 3-Line to 8-Line Decoder / 54HC138 Datasheet
Recommendation Recommendation Datasheet 54HC138 Datasheet




54HC138
High Speed CMOS Logic – 54HC138
3-Line to 8-Line Decoder / Demultiplexer in bare die form
Rev 1.0
23/11/17
Description
Features:
The 54HC138 is fabricated using a 2.5µm 5V CMOS
process with the same high speed performance of LSTTL
combined with CMOS low power consumption. Inputs are
compatible with standard CMOS outputs and LSTTL
outputs by using pull-up resistors. The device decodes a
three–bit Address to one–of–eight active–low outputs.
Featuring three Chip Select inputs, two active–low & one
active–high to facilitate the demultiplexing, cascading, and
chip–select ing functions. The demultiplexing function uses
the Address inputs to select desired device output; one of
the Chip Selects is used as a data input while the other
Chip Selects are held in their active states.
ƒ Output Drive Capability: 10 LSTTL Loads
ƒ Low Input Current: 1µA
ƒ Outputs directly interface CMOS, NMOS and TTL
ƒ Operating Voltage Range: 2V to 6V
ƒ CMOS High Noise Immunity
ƒ Function compatible with 54LS138
ƒ Full Military Temperature Range.
Ordering Information
Die Dimensions in µm (mils)
The following part suffixes apply:
ƒ No suffix - MIL-STD-883 /2010B Visual Inspection
1450 (57)
ƒ H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
ƒ K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For more information on LAT flows please see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
Supply Formats:
Mechanical Specification
ƒ Default – Die in Waffle Pack (400 per tray capacity)
ƒ Sawn Wafer on Tape – On request
ƒ Unsawn Wafer – On request
ƒ Die Thickness <> 350µm(15 Mils) – On request
ƒ Assembled into Ceramic Package – On request
Die Size (Unsawn)
Minimum Bond Pad Size
Die Thickness
Top Metal Composition
Back Metal Composition
1450 x 1500
57 x 59
µm
mils
100 x 100
4x4
µm
mils
350 (±20)
13.78 (±0.79)
µm
mils
Al 1%Si 1.1µm
N/A – Bare Si
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54HC138
High Speed CMOS Logic – 54HC138
d
Pad Layout and Functions
Rev 1.0
23/11/17
DIE ID
14 13 12 11
15
10
16
19
8
2
37
456
0,0
1450µm (57.09 mils)
Truth Table
PAD
FUNCTION
COORDINATES (mm)
XY
1
A0
0.149
0.823
2
A1
0.149
0.409
3
A2
0.111
0.239
4
CS2
0.446
0.129
5
CS3
0.723
0.129
6
CS1
1.004
0.129
7
Y7
1.195
0.203
8
GND
1.217
0.566
9
Y6
1.207
0.832
10 Y5
1.197
1.204
11 Y4
1.000
1.294
12 Y3
0.827
1.294
13 Y2
0.653
1.294
14 Y1
0.479
1.294
15 Y0
0.178
1.238
16 VCC
0.147
0.980
CONNECT CHIP BACK TO VCC OR FLOAT
INPUTS
OUTPUTS
CS1 CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H X X XHHHHHHHH
X H X X X XHHHHHHHH
L X X X X XHHHHHHHH
H L L L L L LHHHHHHH
H L L L L HHLHHHHHH
H L L L H L HHLHHHHH
H L L L HHHHHLHHHH
H L L H L L HHHHLHHH
H L L H L HHHHHHLHH
H L L HH L HHHHHHLH
H L L HHHHHHHHHHL
H = High level (steady state)
L = Low level (steady state)
X = Don’t care
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