Document
TP65H070L Series
650V GaN FET PQFN Series
Preliminary
Description
The TP65H070L 650V, 72mΩ Gallium Nitride (GaN) FET are normally-off devices. It combines state-of-the-art high voltage GaN HEMT and low voltage silicon MOSFET technologies—offering superior reliability and performance.
Transphorm GaN offers improved efficiency over silicon, through lower gate charge, lower crossover loss, and smaller reverse recovery charge.
Related Literature
AN0009: Recommended External Circuitry for GaN FETs AN0003: Printed Circuit Board Layout and Probing AN0010: Paralleling GaN FETs
Ordering Information
Part Number
Package
TP65H070LDG TP65H070LSG
8 x 8mm PQFN 8 x 8mm PQFN
Package Configuration
Drain
Source
TP65H070LDG 8x8 PQFN
(bottom view)
D
S G
TP65H070LSG 8x8 PQFN
(bottom view)
S
D G
Features
JEDEC qualified GaN technology Dynamic RDS(on)eff production tested Robust design, defined by
— Intrinsic lifetime tests — Wide gate safety margin — Transient over-voltage capability Very low QRR Reduced crossover loss RoHS compliant and Halogen-free packaging
Benefits
Improves efficiency/operation frequencies over Si Enables AC-DC bridgeless totem-pole PFC designs
— Increased power density — Reduced system size and weight — Overall lower system cost Easy to drive with commonly-used gate drivers GSD pin layout improves high speed design
Applications
Datacom Broad industrial PV inverter Servo motor
Key Specifications
VDSS (V) V(TR)DSS (V) RDS(on)eff (mΩ) max*
650 800 85
QRR (nC) typ
90
QG (nC) typ
10
* Dynamic on-resistance; see Figures 5 and 6
Cascode Schematic Symbol
February 17, 2019 tp65h070l.0
Cascode Device Structure
© 2018 Transphorm Inc. Subject to change without notice. 1
TP65H070L Series — Preliminary
Absolute Maximum Ratings (Tc=25°C unless otherwise stated.)
Symbol
Parameter
VDSS
Drain to source voltage (TJ = -55°C to 150°C)
V(TR)DSS
Transient drain to source voltage a
VGSS
Gate to source voltage
PD
Maximum power dissipation @TC=25°C
Continuous drain current @TC=25°C b ID
Continuous drain current @TC=100°C b
IDM
Pulsed drain current (pulse width: 10µs)
(di/dt)RDMC
Reverse diode di/dt, repetitive c
(di/dt)RDMT
Reverse diode di/dt, transient d
TC Operating temperature
TJ
TS
Storage temperature
Case Junction
TSOLD
Soldering peak temperature e
Notes: a. In off-state, spike duty cycle D<0.01, spike duration <1µs b. For increased stability at high current operation, see Circuit Implementation on page 3 c. Continuous switching operation d. ≤300 pulses per second for a total duration ≤20 minutes e. For 10 sec., 1.6mm from the case
Limit Value 650 800 ±20 96 25 16 120 1200 2600
-55 to +150 -55 to +150 -55 to +150
260
Unit
V
W A A A A/µs A/µs °C °C °C °C
Thermal Resistance
Symbol
Parameter
Maximum
Unit
RΘJC
Junction-to-case
1.3
°C/W
RΘJA
Junction-to-ambient f
62
°C/W
Notes: f. Device on one layer epoxy PCB for drain connection (vertical and without air stream cooling, with 6cm2 copper area and 70µm thickness)
February 17, 2019 tp65h070l.0
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TP65H070L Series — Preliminary
Circuit Implementation
Simplified Half-bridge Schematic
Efficiency vs Output Power
Recommended gate drive: (0V, 12V) with RG(tot) = 40-60Ω, where RG(tot) = RG + RDRIVER
Gate Ferrite Bead (FB1)
Required DC Link RC Snubber (RCDCL) a
Recommended Switching Node RC Snubber (RCSN) b, c
MMZ1608S181ATA00
[10nF + 8Ω] x 2
33pF + 15Ω
Notes: a. RCDCL should be placed as close as possible to the drain pin b. A switching node RC snubber (C, R) is recommended for high switching currents (>70% of IRDMC1 or IRDMC2; see page 5 for IRDMC1 and IRDMC2) c. IRDM values can be increased by increasing RG and CSN
February 17, 2019 tp65h070l.0
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TP65H070L Series — Preliminary
Electrical Parameter (TJ=25°C unless otherwise stated)
Symbol
Parameter
Min Typ
Forward Device Characteristics V(BL)DSS Drain-source voltage VGS(th) Gate threshold voltage
RDS(on)eff Drain-source on-resistance a
650
—
3.3
4
—
72
—
148
IDSS Drain-to-source leakage current
—
3
—
12
Gate-to-source forward leakage current
—
—
IGSS
Gate-to-source reverse leakage current
—
—
CISS Input capacitance COSS Output capacitance CRSS Reverse transfer capacitance
—
600
—
90
—
4
CO(er) Output capacitance, energy related b
—
135
CO(tr) Output capacitance, time related c
—
220
QG Total gate charge QGS Gate-source charge
—
10
—
3.5
QGD Gate-drain charge
—
3
QOSS Output charge
—
85
tD(on) Turn-on delay
—
27
tR
Rise time
—
7.5
tD(off) Turn-off delay
—
60
tF
Fall time
—
5
Notes: a. Dynamic on-resistance; see Figures 5 and 6 for test circuit and conditions b. Equivalent capacitance to give same stored energy as VDS rises from 0V to 400V c. Equivalent capacitance to give same charging time as VDS r.