IS67WVH8M8ALL

8M x 8 HyperRAM™ IS66WVH8M8ALL/BLL IS67WVH8M8ALL/BLL 6(37(0%(5 201 Overview The IS66/67WVH8M8ALL/BLL are integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and Automotive applications. Distinctive Characteristics HyperBusTM Low Signal Count Interface  3.0V I/O, 11 bus signals – Single ended clock (CK)  1.8V I/O, 12 bus signals – Differential clock (CK, CK#)  Chip Select (CS#)  8-bit data bus (DQ[7:0])  Read-Write Data Strobe (RWDS) – Bidirectional Data Strobe / Mask – Output at the start of all transactions to indicate refresh latency – Output during read transactions as Read Data Strobe – Input during write transactions as Write Data Mask  RWDS DCARS Timing ...