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dsPIC33CH64MP502 Dataheets PDF



Part Number dsPIC33CH64MP502
Manufacturers Microchip
Logo Microchip
Description 16-Bit Digital Signal Controllers
Datasheet dsPIC33CH64MP502 DatasheetdsPIC33CH64MP502 Datasheet (PDF)

dsPIC33CH128MP508 FAMILY 28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating Conditions • 3V to 3.6V, -40°C to +125°C: - Main Core: DC to 90 MIPS - Secondary Core: DC to 100 MIPS • 3V to 3.6V, -40°C to +150°C: - Main Core: DC to 60 MIPS - Secondary Core: DC to 60 MIPS Core: Dual 16-Bit dsPIC33CH CPU • Main/Secondary Core Operation • Independent Peripherals for Main Core and Secondary Core • Dual Partition for Secondar.

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dsPIC33CH128MP508 FAMILY 28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating Conditions • 3V to 3.6V, -40°C to +125°C: - Main Core: DC to 90 MIPS - Secondary Core: DC to 100 MIPS • 3V to 3.6V, -40°C to +150°C: - Main Core: DC to 60 MIPS - Secondary Core: DC to 60 MIPS Core: Dual 16-Bit dsPIC33CH CPU • Main/Secondary Core Operation • Independent Peripherals for Main Core and Secondary Core • Dual Partition for Secondary PRAM LiveUpdate • Configurable Shared Resources for Main Core and Secondary Core • Main Core with 64-128 Kbytes of Program Flash with ECC and 16K RAM • Secondary Core with 24 Kbytes of Program RAM (PRAM) with ECC and 4K Data Memory RAM • Fast Six-Cycle Divide • Message Boxes and FIFO to Communicate Between Main and Secondary (MSI) • Code Efficient (C and Assembly) Architecture • 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle, Mixed-Sign MUL Plus Hardware Divide • 32-Bit Multiply Support • Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response • Zero Overhead Looping Clock Management • Internal Oscillator • Programmable PLLs and Oscillator Clock Sources • Main Reference Clock Output • Secondary Reference Clock Output • Fail-Safe Clock Monitor (FSCM) • Fast Wake-up and Start-up • Backup Internal Oscillator • LPRC Oscillator Power Management • Low-Power Management Modes (Sleep, Idle, Doze) • Integrated Power-on Reset and Brown-out Reset High-Resolution PWM with Fine Edge Placement • Up to 12 PWM Pairs: - Four pairs for Main - Eight pairs for Secondary • 250 ps PWM Resolution • Applications Include: - DC/DC Converters - AC/DC power supplies - Uninterruptable Power Supply (UPS) - Motor Control: BLDC, PMSM, SR, ACIM Timers/Output Compare/Input Capture • Two General Purpose 16-Bit Timers: - One each for Main and Secondary • Peripheral Trigger Generator (PTG) Module: - One module for Main - Secondary can interrupt on select PTG sources - Useful for automating complex sequences • 12 SCCP Modules: - Eight modules for Main - Four modules for Secondary - Timer, Capture/Compare and PWM Modes - 16 or 32-bit time base - 16 or 32-bit capture - Four-deep capture buffer - Fully Asynchronous Operation, Available in Sleep Modes  2017-2023 Microchip Technology Inc. DS70005319E-page 1 dsPIC33CH128MP508 FAMILY Advanced Analog Features • Four ADC Modules: - One module for Main core - Three modules for Secondary core - 12-bit, 3.5 Msps ADC - Up to 18 conversion channels • Four DAC/Analog Comparator Modules: - One module for Main core - Three modules for Secondary core - 12-bit DACs with hardware slope compensation - 15 ns analog comparators • Three PGA Modules: - Three modules for Secondary core - Can be read by Host ADC - Option to interface with Host ADC • Shared DAC/Analog Output: - DAC/analog comparator outputs - PGA outputs Communication Interfaces • Three UART Modules: - Two modules for Main core - One module for Secondary core - Support for LIN/J2602 protocols • Three 4-Wire SPI/I2S Modules: - Two modules for Main core - One module for Secondary core • CAN Flexible Data-Rate (FD) Module for the MainCore • Three I2C Modules: - Two modules for Main - One module for Secondary - Support for SMBus Other Features • PPS to Allow Function Remap • Programmable Cyclic Redundancy Check (CRC) for the Main • Two SENT Modules for the Main Direct Memory Access (DMA) • Eight DMA Channels: - Six DMA channels available for the Main core - Two DMA channels available for the Secondary core Debugger Development Support • In-Circuit and In-Application Programming • Simultaneous Debugging Support for Main and Secondary Cores • Main Only Debug and Secondary Only Debug Support • Main with Three Complex, Five Simple Breakpoints and Secondary with One Complex, Two Simple Breakpoints • IEEE 1149.2 Compatible (JTAG) Boundary Scan • Trace Buffer and Run-Time Watch Safety Features • DMT (Deadman Timer) • ECC (Error Correcting Code) • WDT (Watchdog Timer) • CodeGuard™ Security • CRC (Cyclic Redundancy Check) • Two-Speed Start-up • Fail-Safe Clock Monitoring • Backup FRC (BFRC) • Capless Internal Voltage Regulator • Virtual Pins for Redundancy and Monitoring Functional Safety Readiness – ISO 26262/ IEC 61508/IEC 60730 • To learn about the Functional Safety Readiness of this device family and various Functional Safety standards an application can target using this device family, visit www.microchip.com/ dsPIC33-Functional-Safety Qualification and Class B Support • AEC-Q100 REVG (Grade 1: -40°C to +125°C) Compliant • Class B Safety Library, IEC 60730 DS70005319E-page 2  2017-2023 Microchip Technology Inc. dsPIC33CH128MP508 FAMILY TABLE 1: MAIN AND SECONDARY CORE FEATURES Feature Main Core Secondary Core Core Frequency 90 MIP.


dsPIC33CH128MP508 dsPIC33CH64MP502 dsPIC33CH128MP502


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