dsPIC33CH128MP208

dsPIC33CH128MP508 FAMILY 28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating Conditions 3V to 3.6V, -40°C to +125°C: - Main Core: DC to 90 MIPS - Secondary Core: DC to 100 MIPS 3V to 3.6V, -40°C to +150°C: - Main Core: DC to 60 MIPS - Secondary Core: DC to 60 MIPS Core: Dual 16-Bit dsPIC33CH CPU Main/Secondary Core Operation Independent Peripherals for Main Core and Secondary Core Dual Partition for Secondary PRAM LiveUpdate Configurable Shared Resources for Main Core and Secondary Core Main Core with 64-128 Kbytes of Program Flash with ECC and 16K RAM Secondary Core with 24 Kbytes of Program RAM (PRAM) with ECC and 4K Data Memory RAM Fast Six-Cycle Divide Message Boxes and FIFO to Communicate Between Main and Secondary (MSI) Code Efficient (C and Assembly) Architecture 40-Bit Wide Accumulators Single-Cycle (MAC/MPY) with Dual Data Fetch Single-Cycle, Mixed-Sign MUL Plus Hardware Divide 32-Bit Multiply Support Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response Zero Overhead Looping Clock Management Internal Oscillator Programmable PLLs and Oscillator Clock Sources Main Reference Clock Output Secondary Reference Clock Output Fail-Safe Clock Monitor (FSCM) Fast Wake-up and Start-up Backup Internal Oscillator LPRC Oscillator Power Management Low-Power Management Modes (Sleep, Idle, Doze) Integra...