Cortex-M33 coprocessor. LPC55S69 Datasheet

LPC55S69 coprocessor. Datasheet pdf. Equivalent


Part LPC55S69
Description 32-bit Arm Cortex-M33 coprocessor
Feature LPC55S6x 32-bit Arm Cortex®-M33; M33 coprocessor, TrustZone, PowerQuad, CASPER, 320 KB SRAM; 640 KB.
Manufacture NXP
Datasheet
Download LPC55S69 Datasheet


LPC55S6x 32-bit Arm Cortex®-M33; M33 coprocessor, TrustZone LPC55S69 Datasheet
Recommendation Recommendation Datasheet LPC55S69 Datasheet




LPC55S69
LPC55S6x
32-bit Arm Cortex®-M33; M33 coprocessor, TrustZone,
PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS,
Flexcomm Interface, SDIO, 32-bit counter/ timers,
SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,
Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG
Rev. 1.9 — 10 February 2020
Product data sheet
1. General description
The LPC55S6x is an ARM Cortex-M33 based microcontroller for embedded applications.
These devices include an ARM Cortex-M33 coprocessor, CASPER Crypto/FFT engine,
PowerQuad hardware accelerator for DSP functions, up to 320 KB of on-chip SRAM, up
to 640 KB on-chip flash, PRINCE module for on-the-fly flash encryption/decryption,
high-speed and full-speed USB host and device interface with crystal-less operation for
full-speed, SD/MMC/SDIO interface, five general-purpose timers, one SCTimer/PWM,
one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer
(WWDT), nine flexible serial communication peripherals (which can be configured as a
USART, SPI, high speed SPI, I2C, or I2S interface), Programmable Logic Unit (PLU), one
16-bit 1.0 Msamples/sec ADC, comparator, and temperature sensor.
The ARM Cortex-M33 provides a security foundation, offering isolation to protect valuable
IP and data with TrustZone® technology. It simplifies the design and software
development of digital signal control systems with the integrated digital signal processing
(DSP) instructions. To support security requirements, the LPC55S6x also offers support
for secure boot, HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug
authentication, and TBSA compliance.
2. Features and benefits
ARM Cortex-M33 core (CPU0, r0p3):
Running at a CPU frequency of up to 150 MHz (device revision 1B only).
TrustZone®, Floating Point Unit (FPU) and Memory Protection Unit (MPU).
ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug with eight breakpoints and four watch points. Includes Serial
Wire Output for enhanced debug capabilities.
System tick timer.
ARM Cortex-M33 co-processor (CPU1, r0p3):
Running at a CPU frequency of up to 150 MHz (device revision 1B only).
The configuration of this instance does not include MPU, FPU, DSP, ETM, and
Trustzone.
System tick timer.



LPC55S69
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
LPC55S6x
Product data sheet
CASPER Crypto co-processor is provided to enable hardware acceleration for various
functions required for certain asymmetric cryptographic algorithms, such as, Elliptic
Curve Cryptography (ECC).
PowerQuad hardware accelerator for (fixed and floating point unit) CMSIS DSP
functions with support of SDK software API faster execution of ARM CMSIS instruction
set.
On-chip memory:
Up to 640 KB on-chip flash program memory with flash accelerator and 512 byte
page erase and write.
Up to 320 KB total SRAM consisting of 32 KB SRAM on Code Bus, 272 KB SRAM
on System Bus (272 KB is contiguous), and additional 16 KB USB SRAM on
System Bus which can be used by the USB interface or for general purpose use.
PRINCE module for real-time encryption of data being written to on-chip flash and
decryption of encrypted flash data during read to allow asset protection, such as
securing application code, and enabling secure flash update.
On-chip ROM bootloader supports:
Booting of images from on-chip flash
Supports CRC32 image integrity checking.
Supports flash programming through In System Programming (ISP) commands
over following interfaces: USB0/1 interfaces using HID Class device, UART
interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9)
using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)
ROM API functions: Flash programming API, Power control API, and Secure
firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files).
Supports booting of images from PRINCE encrypted flash regions.
Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1
(RSA-4096).
Supports setting a sealed part to Fault Analysis mode through Debug
authentication.
Secure Boot support:
Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic
signature verification.
Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).
Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).
Uses x509 certificate format to validate image public keys.
Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys,
Root of Trust establishment by storing the SHA-256 hash digest of the hashes of
four RoT public keys in protected flash region (PFR).
Supports anti-rollback feature using image key revocation and supports up to 16
Image key certificates revocations using Serial Number field in x509 certificate.
Serial interfaces:
Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7
and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which
is dedicated for high-speed SPI) can be selected by software to be a USART, SPI,
I2C, and I2S interface. Each Flexcomm Interface includes a FIFO that supports
USART, SPI, and I2S. A variety of clocking options are available to each Flexcomm
Interface, including a shared fractional baud-rate generator, and time-out
feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I2S.
All information provided in this document is subject to legal disclaimers.
Rev. 1.9 — 10 February 2020
© NXP Semiconductors N.V. 2020. All rights reserved.
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