Document
MOSFETs Silicon N-channel MOS (U-MOS-H)
SSM6K810R
1. Applications
• Power Management Switches • DC-DC Converters
2. Features
(1) AEC-Q101 qualified (Note 1) (2) 175 MOSFET (3) 4.5-V drive (4) Low drain-source on-resistance
: RDS(ON) = 65 mΩ (typ.) (@VGS = 4.5 V) RDS(ON) = 51 mΩ (typ.) (@VGS = 10 V)
Note 1: For detail information, please contact our sales.
3. Packaging and Pin Assignment
TSOP6F
SSM6K810R
1: Drain 2: Drain 3: Gate 4: Source 5: Drain 6: Drain
©2018-2020 Toshiba Electronic Devices & Storage Corporation
1
Start of commercial production
2019-03
2020-09-24 Rev.4.0
SSM6K810R
4. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 )
Characteristics
Symbol
Rating
Unit
Drain-source voltage
VDSS
100
V
Gate-source voltage
VGSS
±20
Drain current (DC)
(Note 1)
ID
3.5
A
Drain current (pulsed)
(t ≤ 10 ms) (Note 1), (Note 2)
IDP
14
Power dissipation
(Note 3)
PD
1.5
W
Power dissipation
(t ≤ 10 s)
(Note 3)
PD
3
Single-pulse avalanche energy
(Note 4)
EAS
21.4
mJ
Channel temperature
(Note 5)
Tch
175
Storage temperature
(Note 5)
Tstg
-55 to 175
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: Ensure that the channel temperature does not exceed 175 . Note 2: Pulse width ≤ 10 ms, Duty ≤ 1 % Note 3: Device mounted on a 25.4 mm × 25.4 mm × 1.6 mm FR4 glass epoxy board (Cu pad: 645 mm2) Note 4: VDD = 25 V, Tch = 25 (Initial state), L = 1 mH, RG = 25 Ω Note 5: The definitions of the absolute maximum channel and storage temperatures are qualified per AEC-Q101.
Note: Note:
Note:
This transistor is sensitive to electrostatic discharge and should be handled with care. The MOSFETs in this device are sensitive to electrostatic discharge. When handling this device, the worktables, operators, soldering irons and other objects should be protected against anti-static discharge. The channel-to-ambient thermal resistance, Rth(ch-a), and the drain power dissipation, PD, vary according to the board material, board area, board thickness and pad area. When using this device, be sure to take heat dissipation fully into account.
©2018-2020 Toshiba Electronic Devices & Storage Corporation
2
2020-09-24 Rev.4.0
SSM6K810R
5. Electrical Characteristics 5.1. Static Characteristics (Unless otherwise specified, Ta = 25 )
Characteristics
Symbol
Test Condition
Min Typ. Max Unit
Gate leakage current
IGSS VDS = 0 V, VGS = ±16 V
±10
µA
Drain cut-off current
IDSS VDS = 100 V, VGS = 0 V
10
Drain-source breakdown voltage
V(BR)DSS ID = 10 mA, VGS = 0 V
100
V
Drain-source breakdown voltage
(Note 1) V(BR)DSX ID = 10 mA, VGS = -20 V
80
Gate threshold voltage
(Note 2) Vth VDS = 10 V, ID = 0.1 mA
1.5
2.5
Drain-source on-resistance
(Note 3) RDS(ON) ID = 1 A, VGS = 4.5 V
65
92
mΩ
ID = 2 A, VGS = 10 V
51
69
Note 1: If a reverse bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drainsource breakdown voltage is lowered in this mode.
Note 2: Let Vth be the voltage applied between gate and source that causes the drain current (ID) to below (0.1 mA for this device). Then, for normal switching operation, VGS(ON) must be higher than Vth, and VGS(OFF) must be lower than Vth. This relationship can be expressed as: VGS(OFF) < Vth < VGS(ON). Take this into consideration when using the device.
Note 3: Pulse measurement.
5.2. Dynamic Characteristics (Unless otherwise specified, Ta = 25 )
Characteristics Input capacitance Reverse transfer capacitance Output capacitance Switching time (rise time) Switching time (turn-on time) Switching time (fall time) Switching time (turn-off time)
5.3. Switching Time Test Circuit
Symbol
Test Condition
Min Typ. Max Unit
Ciss VDS = 15 V , VGS = 0 V, Crss f = 1 MHz
430
pF
22
Coss
160
tr VDD = 30 V, ID = 1.0 A,
9
ns
ton
VGS = 0 to 4.5 V, RG = 50 Ω Duty ≤ 1 %, Input: tr, tf < 5 ns,
21
tf Common source,
7.0
toff See chapter 5.3.
16
Fig. 5.3.1 Switching Time Test Circuit
Fig. 5.3.2 Input Waveform/Output Waveform
5.4. Gate Charge Characteristics (Unless otherwise specified, Ta = 25 )
Characteristics
Total gate charge (gate-source plus gate-drain) Gate-source charge 1 Gate-drain charge
Symbol
Test Condition
Qg Qgs1 Qgd
VDD = 50 V, ID = 2.0 A, VGS = .