high-side driver. VNQ7003SY Datasheet

VNQ7003SY driver. Datasheet pdf. Equivalent


STMicroelectronics VNQ7003SY
VNQ7003SY
Quad-channel high-side driver with 16-bit SPI interface for
automotive applications
Datasheet - production data
– Undervoltage shutdown
– Overvoltage clamp
– Latch-off or programmable time limited
auto restart (power limitation and
overtemperature shutdown)
– Load dump protected
– Protection against loss of ground
Features
Channel
0–1
2–3
VCC
28 V
28 V
RON(typ)
25 m
7 m
ILIMH(typ)
35 A
80 A
AEC-Q100 qualified
General
– 16-bit ST-SPI for full diagnostic with 8 bits
Short Frame option
– Programmable Bulb/LED mode for
ch. 0-1
– Advanced limp home functions for robust
fail-safe system
– Very low standby current
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– Control through direct inputs and / or SPI
– Compliant with European directive
2002/95/EC
Diagnostic functions
– Multiplex proportional load current sense
– Synchronous diagnostic of over load and
short to GND, output shorted to VCC and
OFF-state open-load
– Programmable case overtemperature
warning
Protection
– Two levels load current limitation
– Self limiting of fast thermal transients
Description
The VNQ7003SY is a device made using
STMicroelectronics® VIPower® technology. It is
intended for driving resistive or inductive loads
directly connected to ground. The device is
protected against voltage transient on VCC pin.
An 8 bit short frame access to output control
registers is provided allowing PWM control
through SPI with high granularity.
An analog current feedback for each channel is
connected to the CURRENT-SENSE pin via a
multiplexer. The device detects open-load in OFF-
state conditions.
Real time diagnostic is available through the SPI
bus (open-load, output short to VCC,
overtemperature, communication error, power
limitation or latch off).
Output current limitation protects the device in an
over load condition. The device can limit the
dissipated power to a safe level up to thermal
shutdown intervention. Thermal shutdown can be
configured as latched off or programmable time
limited auto restart.
The device enters a limp home mode in case of
loss of digital supply (VDD), reset of digital
memory or watchdog monitoring time-out event.
In this mode states of channel 0, 1, 2 or 3 are
respectively controlled by four dedicated pins IN0,
IN1, IN2 and IN3. Channel 0 and 1 can be
programmed via SPI for load type (BULB/ LED
mode).
December 2018
This is information on a product in full production.
DS11059 Rev 8
1/102
www.st.com


VNQ7003SY Datasheet
Recommendation VNQ7003SY Datasheet
Part VNQ7003SY
Description Quad-channel high-side driver
Feature VNQ7003SY; VNQ7003SY Quad-channel high-side driver with 16-bit SPI interface for automotive applications Datas.
Manufacture STMicroelectronics
Datasheet
Download VNQ7003SY Datasheet




STMicroelectronics VNQ7003SY
Contents
Contents
VNQ7003SY
1
2
3
4
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Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Device interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1 Startup transition phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Fail Safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.6 Sleep mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.7 Sleep mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.8 Battery undervoltage mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.9 Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Pre-warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Junction overtemperature (OT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Power limitation (PL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.2 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.3 SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.1 SDI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.2 SDO format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.3 Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.4 Special commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.1 Global Status byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.3 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DS11059 Rev 8



STMicroelectronics VNQ7003SY
VNQ7003SY
Contents
4.3.4 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4 Output switching slopes control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.5 Output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.6.1 Address 0x00h — Control Register (CTLR) . . . . . . . . . . . . . . . . . . . . . 40
4.6.2 Address 0x01h — Direct Input Enable Control Register (DIENCR) . . . 41
4.6.3 Address 0x02h — Open-load OFF-State Control Register (OLOFFCR) 42
4.6.4 Address 0x03h — Channel Control Register (CCR) . . . . . . . . . . . . . . . 42
4.6.5
Address 0x04h — Fast Switching Configuration Register (FASTSWCR)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.6.6
Address 0x06h — current sense Multiplexer Control Register
(CSMUXCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.6.7 Address 0x07h — SPI Output Control Register (SOCR) . . . . . . . . . . . . 43
4.6.8
Address 0x08h — Channel Latch OFF Timer Control Register (ch0, ch1)
(CHLOFFTCR0,1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6.9
Address 0x09h — Channel Latch OFF Timer Control Register (ch2, ch3)
(CHLOFFTCR2,3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1 Analogue diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2 Digital diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2.1 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3 Over load (VDS high voltage, Over Load (OVL)) . . . . . . . . . . . . . . . . . . . 48
5.4 Open-load ON-state detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.5 Open-load OFF-state detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.6 Address 0x2Fh — DIENSR: Direct Input Status register . . . . . . . . . . . . . 50
5.7 Address 0x30h — Channel Feedback Status Register (CHFBSR) . . . . . 51
5.8 Address 0x31h — Open-load OFF-State / Stuck to VCC Status Register
(OLOFFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.9 Address 0x32h — Channels latch-off status register (CHLOFFSR) . . . . 52
5.10 Address 0x33h — VDS Feedback Status Register (VDSFSR) . . . . . . . . 52
5.11 Address 0x34h — Generic Status Register (GENSR) . . . . . . . . . . . . . . . 53
5.12 Address 0x3Fh — Configuration Register (CONFIG) . . . . . . . . . . . . . . . 53
6 Programmable blanking window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2 Blanking window values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DS11059 Rev 8
3/102
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