NDB16P

1Gb (x16) – DDR2 Synchronous DRAM 64M x 16 bit DDR2 Synchronous DRAM Overview The NDB16P is a high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous dynamic random-access memory (SDRAM) containing 1024 Mbits in a 16-bit wide data I/Os. It is internally configured as an 8-bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination (ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style. Accesses begin with the registration of a...