Document
dsPIC33EPXXXGS70X/80X FAMILY
16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
Operating Conditions
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
Flash Architecture
• Dual Partition Flash Program Memory with Live Update: - Supports programming while operating - Supports partition soft swap
Core: 16-Bit dsPIC33E CPU
• Code-Efficient (C and Assembly) Architecture • Two 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle Mixed-Sign MUL plus
Hardware Divide • 32-Bit Multiply Support • Four Additional Working Register Sets (reduces
context switching)
Clock Management
• ±0.9% Internal Oscillator • Programmable PLLs and Oscillator Clock Sources • Fail-Safe Clock Monitor (FSCM) • Independent Watchdog Timer (WDT) • Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle, Doze.