CLOCK MULTIPLIER. ICS511 Datasheet

ICS511 MULTIPLIER. Datasheet pdf. Equivalent

ICS511 Datasheet
Recommendation ICS511 Datasheet
Part ICS511
Description PLL CLOCK MULTIPLIER
Feature ICS511; LOCO™ PLL CLOCK MULTIPLIER DATASHEET ICS511 Description The ICS511 LOCOTM is the most cost effecti.
Manufacture IDT
Datasheet
Download ICS511 Datasheet




IDT ICS511
LOCO™ PLL CLOCK MULTIPLIER
DATASHEET
ICS511
Description
The ICS511 LOCOTM is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to 200
MHz.
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
The device also has an output enable pin which
tri-states the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
Features
Packaged as 8-pin SOIC or die
Pb (lead) free package
Upgrade of popular ICS501 with:
- changed multiplier table
- faster operating frequencies
- output duty cycle at VDD/2
Zero ppm multiplication error
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 200 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 200 MHz
Mask option for nine selectable frequencies
Operating voltage of 3.3 V or 5 V
Tri-state output for board level testing
Industrial temperature version available
Advanced, low power CMOS process
Block Diagram
VDD
S1:0 2
Crystal or
Clock input
X1/ICLK
X2
Crystal
O s c illa to r
Optional crystal capacitors
PLL Clock
M u ltip lie r
Circuitry
and ROM
GND
OE
CLK
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
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IDT ICS511
ICS511
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
X1/ I CLK
VDD
GND
S1
1
2
3
4
8 X2
7 OE
6 S0
5 CLK
8 Pi n ( 150 mi l ) SOI C
Clock Output Table
S1 S0
00
0M
01
M0
MM
M1
10
1M
11
CLK
4X input
5.333X input
5X input
2.5X input
2X input
3.333X input
6X input
3X input
8X input
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output
20 24 30 32 33.33 37.5 40 48
Input
10 12 10 16 16.66 15 10 12
Selection (S1, S0) M, M M, M 1, M M, M M, M M, 0 0, 0 0, 0
50 60 64
20 10 16
M, 0 1, 0 0, 0
Output
66.66 72 75 80 83.33 90 100 120
Input
20 12 25 10 25 15 20 15
Selection (S1, S0) M, 1 1, 0 1, M 1, 1 M, 1 1, 0 0, 1 1, 1
Pin Descriptions
125 133.3 150
25 25 25
0, 1 0, M 1, 0
Pin Pin
Number Name
1 XI/ICLK
2 VDD
3 GND
4 S1
5 CLK
Pin
Type
Input
Power
Power
Tri-level Iinput
Output
Pin Description
Crystal connection or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Select 1 for output clock. Connect to GND or VDD or float.
Clock output per table above.
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
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IDT ICS511
ICS511
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin
Number
6
7
Pin
Name
S0
OE
8 X2
Pin
Type
Tri-level Input
Input
Output
Pin Description
Select 0 for output clock. Connect to GND or VDD or float.
Output enable. Tri-states CLK output when low. Internal pull-up
resistor.
Crystal connection. Leave unconnected for clock input.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS511 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected close
to the ICS511 to minimize lead inductance. No external
power supply filtering is required for the ICS511.
Series Termination Resistor
A 33terminating resistor can be used next to the CLK
pin for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal (CL
-12 pF)*2. In this equation, CL= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
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