Differential-to-LVCMOS Translator/Buffer. 83023I Datasheet

83023I Translator/Buffer. Datasheet pdf. Equivalent

83023I Datasheet
Recommendation 83023I Datasheet
Part 83023I
Description Dual 1-TO-1 Differential-to-LVCMOS Translator/Buffer
Feature 83023I; Dual, 1-TO-1 Differential-to-LVCMOS Translator/Buffer 83023I Data Sheet GENERAL DESCRIPTION The 83.
Manufacture IDT
Datasheet
Download 83023I Datasheet




IDT 83023I
Dual, 1-TO-1
Differential-to-LVCMOS Translator/Buffer
83023I
Data Sheet
GENERAL DESCRIPTION
The 83023I is a dual, 1-to-1 Differential-to-LVCMOS
Translator/Fanout Buffer.The differential inputs can accept most
differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and
HCSL) and translate into two single-ended LVCMOS outputs.
The small 8-lead SOIC footprint makes this device ideal for use
in applications with limited board space.
Features
Two LVCMOS / LVTTL outputs
Two differential CLKx, nCLKx input pairs
CLK, nCLK pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 350MHz (typical)
Output skew: 60ps (maximum)
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.14ps (typical)
Small 8 lead SOIC package saves board space
3.3V operating supply
-40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
CLK0
nCLK0
CLK1
nCLK1
Q0
Q1
PIN ASSIGNMENT
CLK0
nCLK0
nCLK1
CLK1
1
2
3
4
8 VDD
7 Q0
6 Q1
5 GND
83023I
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
M Package
Top View
©2015 Integrated Device Technology, Inc
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December 14, 2015



IDT 83023I
83023I Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
CLK0
Input Pulldown Non-inverting differential clock input.
2
nCLK0
Input
Pullup Inverting differential clock input.
3
nCLK1
Input
Pullup Inverting differential clock input.
4
CLK1
Input Pulldown Non-inverting differential clock input.
5
GND
Power
Power supply ground.
6 Q1 Output
Single clock output. LVCMOS / LVTTL interface levels.
7 Q0 Output
Single clock output. LVCMOS / LVTTL interface levels.
8 VDD Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
CIN Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
VDD = 3.6V
Minimum
Typical
4
23
51
51
7
Maximum Units
pF
pF
kΩ
kΩ
Ω
©2015 Integrated Device Technology, Inc
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December 14, 2015



IDT 83023I
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
83023I Data Sheet
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions Minimum
VDD Positive Supply Voltage
IDD Positive Supply Current
3.0
Typical
3.3
Maximum
3.6
20
Units
V
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VOH Output High Voltage; NOTE 1
2.6
VOL Output Low Voltage; NOTE 1
0.5
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
V
V
TABLE
3C.
DIFFERENTIAL
DC
CHARACTERISTICS,
V
DD
=
3.3V±0.3V,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical
IIH
IIL
VPP
VCMR
nCLK0, nCLK1
Input High Current
CLK0, CLK1
nCLK0, nCLK1
Input Low Current
CLK0, CLK1
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
VIN = VDD = 3.6V
VIN = VDD = 3.6V
VIN = 0V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
-150
-5
0.15
GND + 0.5
NOTE 1: For single-ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as V .
IH
Maximum
5
150
1.3
VDD - 0.85
Units
µA
µA
µA
µA
V
V
©2015 Integrated Device Technology, Inc
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December 14, 2015







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