REM Switch. fido5200 Datasheet

fido5200 Switch. Datasheet pdf. Equivalent

fido5200 Datasheet
Recommendation fido5200 Datasheet
Part fido5200
Description Real-Time Ethernet Multiprotocol (REM) Switch
Feature fido5200; Data Sheet FEATURES 144-lead CSP_BGA RoHS compliant package −40°C to +85°C industrial temperature ra.
Manufacture Analog Devices
Datasheet
Download fido5200 Datasheet




Analog Devices fido5200
Data Sheet
FEATURES
144-lead CSP_BGA RoHS compliant package
−40°C to +85°C industrial temperature range rating
3.3 V input/output buffers
IEEE 802.3, 10 Mbps/100 Mbps, half and full duplex, IPv6 and
IPv4 communication
2 independent Ethernet ports: 1 MII and 1 RMII interface per
port
Support for all industrial protocols
PROFINET Class B and Class C with fast startup (Version 2.3)
EtherNet/IP with QuickConnect, CIP Sync, and CIP Motion
Modbus TCP
EtherCAT
Ethernet POWERLINK
Host interface transfer rate: 32 bits per 28 ns
Supports EtherCAT cycle times down to 12.5 μs and
PROFINET cycle times down to 31.25 μs
PI Net Load Class III capable
DLR (supervisor and node, announce and beacon based),
MRPD, HSR, PRP, shared device, controller redundancy
IEEE 1588 Version 2 support: ordinary clock; both peer to peer
and end to end transparent clocks, raw frames, and UDP
8 independent timer signals synchronized with an internal
precision timer
4 independently programmable timer signals for timer
capture events or timer output events
4 timer signals create programmable periodic waveforms
synchronized to the internal precision timer
DCP, LLDP, DHCP, RSTP, VLAN, IGMP snooping support
Forwarding table with aging and learning
Drive LEDs for link activity
APPLICATIONS
Industrial automation
Process control
Managed Ethernet switch
Real-Time Ethernet
Multiprotocol (REM) Switch
fido5100/fido5200
FUNCTIONAL BLOCK DIAGRAM
REM SWITCH
TIMER
CONTROL
UNIT
HOST
INTERFACE
BUFFER
MEMORY
INTERRUPT
CONTROL
PORT 1
PORT 2
Figure 1.
GENERAL DESCRIPTION
The fido5100 and fido5200 (REM switch) are programmable
IEEE 802.3 10 Mbps/100 Mbps Ethernet Internet Protocol
Version 6 (IPv6) and Internet Protocol Version 4 (IPv4) switches
that support virtually any Layer 2 or Layer 3 protocol. The
switches are personalized to support the desired protocol by
firmware that is downloaded from a host processor.
The firmware is contained in the real-time Ethernet multiprotocol
(REM) switch driver and is downloaded at power-up. The REM
switch can be ready for network data operation in less than 4 ms to
support fast startup and quick connect type network functionality.
The REM switch devices have the same signal assignments as
defined in this data sheet.
The fido5100 supports the following protocols: PROFINET real
time (RT) and isochronous real time (IRT), EtherNet/IP with
and without device level ring (DLR), Modbus TCP, and
POWERLINK.
The fido5200 supports the following protocols: EtherCAT and
all protocols defined for the fido5100.
The REM switch is intended for use with a host processor.
Network operation is handled using the functions and services
provided in the REM switch driver. The host processor can
implement any protocol stack by integrating it with the REM
switch driver. An example application is shown in Figure 11.
The REM switches are available in a 144-ball chip scale package
ball grid array (CSP_BGA) package.
Note that throughout this data sheet, multifunction pins, such
as A02/ALE, are referred to either by the entire pin name or by
a single function of the pin, for example, ALE, when only that
function is relevant.
Rev. C
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Tel: 781.329.4700 ©2017–2019 Analog Devices, Inc. All rights reserved.
Technical Support
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Analog Devices fido5200
fido5100/fido5200
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
REM Switch Characteristics........................................................ 3
Timing Specifications—Nonmultiplexed Address Data Bus.. 3
Timing Specifications—Multiplexed Address Data Bus ......... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
REVISION HISTORY
8/2019—Rev. B to Rev. C
Change to Features Section, General Description Section, and
Figure 1 .............................................................................................. 1
Changes to Figure 6.......................................................................... 8
Change to Crystal Section and Figure 8 ...................................... 12
Change to Figure 9 and Figure 10 ................................................ 16
Changes to Figure 11, REM Switch Hardware Section, and
Power Section.................................................................................. 17
Changes to Table 13........................................................................ 18
1/2019—Rev. A to Rev. B
Change to tAH Parameter, Table 2.................................................... 3
Changes to Ordering Guide .......................................................... 19
Data Sheet
Theory of Operation ...................................................................... 13
Device Interfaces ........................................................................ 13
Internal Precision Timer ........................................................... 13
Host Interface.............................................................................. 13
Ethernet Interface....................................................................... 16
Applications Information .............................................................. 18
REM Switch Hardware .............................................................. 18
Board Layout............................................................................... 18
Design Considerations .............................................................. 18
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
8/2018—Rev. 0 to Rev. A
Added Core Current Parameter and I/O Current Parameter,
Table 1 .................................................................................................3
Changes to tAS Parameter and tAH Parameter, Table 2...................3
Added Note 2 and Note 3, Table 2; Renumbered Sequentially ...3
Change to Power Dissipation Parameter, Table 4 .........................7
10/2017—Revision 0: Initial Version
Rev. C | Page 2 of 19



Analog Devices fido5200
Data Sheet
fido5100/fido5200
SPECIFICATIONS
REM SWITCH CHARACTERISTICS
Table 1.
Parameter
OPERATING CONDITIONS
Core Voltage
Core Current
Input/Output (I/O) Buffers
I/O Current
PLL Analog Voltage Regulator Power Supply
DC Input Voltage
Output Voltage
Operating Junction Temperature (Industrial)
DC CHARACTERISTICS (I/O STANDARD)
3.3 V LVCMOS
VCC+3V3
Input Voltage
Low (VIL)
High (VIH)
Output Voltage
Low (VOL)
High (VOH)
Output Current
Low (IOL)
High (IOH)
LEAKAGE CURRENT
Input Pin
Tristated I/O Pin
HOST INTERFACE TRANSFER RATE1
Min Typ Max
1.08 1.2
2.97 3.3
1.08 1.2
−0.5
−0.5
−40
1.32
48
3.63
0.035
1.32
+3.8
+3.8
+125
Unit Test Conditions/Comments
V
mA At TA = 85°C
V 3.3 V power supply
mA At TA = 85°C
V
V
V
°C
2.97 3.3
3.63
−0.3 +0.8
2.0 3.6
0.4
2.4
8.2 13.0 16.1
9.2 19.2 30.7
−10
−10
32
+10
+10
V Voltage level applied to the VCC+3V3 signal
V
V
V
V
mA
mA
μA Input voltage (VIN) = 0 V to 3.3 V maximum
μA Output voltage (VOUT) = 0 V to 3.3 V maximum
Bits Per 28 ns
1 Supports EtherCAT cycle times down to 12.5 μs and PROFINET cycle times down to 31.25 μs.
TIMING SPECIFICATIONS—NONMULTIPLEXED ADDRESS DATA BUS
Table 2. Nonmultiplexed Address Data Bus—Read and Write Cycle Timing1, 2, 3
Parameter
Min Typ Max Unit Description
tAS 2
ps Address setup time
tAH 370
ps Address hold time
tCDV 20 ns CS to data valid time
tODV 20 ns Output enable to data valid time
tOEL 20
ns Output enable low time
tCSH 8
ns CS high time
tCSL 20
ns CS low time
tEOE 0
ns CS to output enable time
tCOE 0
ns Output enable high to CS high
tDO 150
ps Output enable to data drive time
tDHZ
110 ps
Output disable to high-Z time
tCHZ
110 ps
CS high to high-Z time
tWES 0
ns CS to write enable
tWEWC
16
ns Write enable to write complete
tWECS
0
ns Write enable high to CS high
tDS 30
ps Data setup to WE high
tDH 30
ps Input data hold after WE high
1 The MBS pin determines whether the host interfaced has multiplexed or separate address and data lines. When MBS = 0, the interface is nonmultiplexed.
2 OE can be taken low before CS. Therefore, tEOE can be a negative value. In this case, a board designer must closely monitor tDO and tCDV to avoid bus contention and
ensure proper data transfer.
3 The read bus cycle terminates when either CS or OE is taken high. Therefore, a negative value for tCOE is acceptable in some circumstances.
Rev. C | Page 3 of 19







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