D Flip-Flops. MM54HC174 Datasheet

MM54HC174 Flip-Flops. Datasheet pdf. Equivalent

MM54HC174 Datasheet
Recommendation MM54HC174 Datasheet
Part MM54HC174
Description Hex D Flip-Flops
Feature MM54HC174; MM54HC174 MM74HC174 Hex D Flip-Flops with Clear January 1988 MM54HC174 MM74HC174 Hex D Flip-Flops .
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National Semiconductor MM54HC174
January 1988
MM54HC174 MM74HC174
Hex D Flip-Flops with Clear
General Description
These edge triggered flip-flops utilize advanced silicon-gate
CMOS technology to implement D-type flip-flops They pos-
sess high noise immunity low power and speeds compara-
ble to low power Schottky TTL circuits This device contains
6 master-slave flip-flops with a common clock and common
clear Data on the D input having the specified setup and
hold times is transferred to the Q output on the low to high
transition of the CLOCK input The CLEAR input when low
sets all outputs to a low state
Each output can drive 10 low power Schottky TTL equiva-
lent loads The MM54HC174 MM74HC174 is functionally
as well as pin compatible to the 54LS174 74LS174 All in-
puts are protected from damage due to static discharge by
diodes to VCC and ground
Connection and Logic Diagrams
Features
Y Typical propagation delay 16 ns
Y Wide operating voltage range 2 – 6V
Y Low input current 1 mA maximum
Y Low quiescent current 80 mA (74HC Series)
Y Output drive 10 LSTTL loads
Dual-In-Line Package
TL F 5318 – 1
Order Number MM54HC174 or MM74HC174
Truth Table
(Each Flip-Flop)
Inputs
Outputs
Clear Clock D
Q
L
XX
L
H uH H
H uL L
H LX Q
H e High level (steady state)
L e Low level (steady state)
X e Don’t Care
u e Transition from low to high level
Q0 e The level of Q before the indicated steady state
input conditions were established
C1995 National Semiconductor Corporation TL F 5318
TL F 5318 – 2
RRD-B30M105 Printed in U S A



National Semiconductor MM54HC174
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK IOK)
DC Output Current per pin (IOUT)
DC VCC or GND Current per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S O Package only
b0 5 to a7 0V
b1 5 to VCCa1 5V
b0 5 to VCCa0 5V
g20 mA
g25 mA
g50 mA
b65 C to a150 C
600 mW
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage VCC
DC Input or Output Voltage
VIN VOUT
Operating Temp Range (TA)
MM HC
MM HC
Min
b
b
Input Rise or Fall Times
tr tf VCCe V
VCCe V
VCCe V
Max
VCC
a
a
Units
V
V
C
C
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TAe25 C
Typ
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C
Guaranteed Limits
Units
VIH Minimum High Level
Input Voltage
V
V
V
V
V
V
VIL Maximum Low Level
Input Voltage
V
V
V
V
V
V
VOH
Minimum High Level VINeVIH or VIL
Output Voltage
lIOUTls mA
V
V
V
V
V
V
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
VOL Maximum Low Level VINeVIH or VIL
Output Voltage
lIOUTls mA
V
V
V
V
V
V
V
V
V
V
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
V
V
IIN
Maximum Input
VINeVCC or GND
V
Current
g
g
V
V
g mA
ICC
Maximum Quiescent VINeVCC or GND
V
Supply Current
IOUTe mA
mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when
designing with this supply Worst case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN
ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used
VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89
2



National Semiconductor MM54HC174
AC Electrical Characteristics VCCe5V TAe25 C CLe15 pF tretfe6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating
Frequency
MHz
tPHL tPLH Maximum Propagation
Delay Clock or Clear to Output
ns
tREM
Minimum Removal Time
Clear to Clock
b ns
tS Minimum Setup Time
Data to Clock
ns
tH Minimum Hold Time
Clock to Data
ns
tW Minimum Pulse Width
Clock or Clear
ns
AC Electrical Characteristics CLe50 pF tretfe6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC TAe25 C
Typ
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C
Guaranteed Limits
Units
fMAX
Maximum Operating
Frequency
V
V
V
MHz
MHz
MHz
tPHL tPLH Maximum Propagation
Delay Clock or Clear to Output
V
V
V
ns
ns
ns
tREM
Minimum Removal Time
Clear to Clock
V
V
V
ns
ns
ns
tS Minimum Setup Time
Data to Clock
V
V
V
ns
ns
ns
tH Minimum Hold Time
Clock to Data
V
V
V
ns
ns
ns
tW Minimum Pulse Width
Clock or Clear
V
V
V
ns
ns
ns
tTLH tTHL Maximum Output Rise
and Fall Time
V
V
V
ns
ns
ns
tr tf Maximum Input Rise and
Fall Time
V
V
V
ns
ns
ns
CPD Power Dissipation
Capacitance Note
per package
pF
CIN Maximum Input
Capacitance
pF
Note 5 CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
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