Buck Regulator. ISL8018 Datasheet

ISL8018 Regulator. Datasheet pdf. Equivalent

ISL8018 Datasheet
Recommendation ISL8018 Datasheet
Part ISL8018
Description 8A Low Quiescent Current High Efficiency Synchronous Buck Regulator
Feature ISL8018; DATASHEET ISL8018 8A Low Quiescent Current High Efficiency Synchronous Buck Regulator FN7889 Rev 0.
Manufacture Renesas
Datasheet
Download ISL8018 Datasheet




Renesas ISL8018
DATASHEET
ISL8018
8A Low Quiescent Current High Efficiency Synchronous Buck Regulator
FN7889
Rev 0.00
September 30, 2015
The ISL8018 is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 8A
continuous output current from a 2.7V to 5.5V input supply.
The output voltage is adjustable from 0.6V to VIN. With an
adjustable current limit, reverse current protection, prebias
start and over-temperature protection, the ISL8018 offers a
highly robust power solution. It uses current control
architecture to deliver fast transient response and excellent
loop stability.
The ISL8018 integrates a pair of low ON-resistance P-channel
and N-channel internal MOSFETs to maximize efficiency and
minimize external component count. 100% duty-cycle
operation allows less than 250mV dropout at 8A output
current. Adjustable frequency and synchronization allow the
ISL8018 to be used in applications requiring low noise.
The ISL8018 can be configured for discontinuous or forced
continuous operation at light load. Forced continuous operation
reduces noise and RF interference while discontinuous mode
provides high efficiency by reducing switching losses at light
loads.
The ISL8018 is offered in a space saving 20 Ld 3x4 QFN lead
free package with exposed pad lead frames for excellent
thermal performance. The complete converter occupies less
than 96.8mm2 area.
See Ordering Information on page 2 for more detail.
Related Literature
UG052 “ISL8018DEMO1Z Demonstration Board User Guide”
UG053 “ISL8018EVAL3Z Evaluation Board User Guide”
Features
• High efficiency synchronous buck regulator with up to 97%
efficiency
• ±10% output voltage margining
• Adjustable current limit
• Start-up with prebiased output
• Internal soft-start - 1ms or adjustable, internal/external
compensation
• Soft-stop output discharge during disabled
• Adjustable frequency from 500kHz to 4MHz - default at
1MHz
• External synchronization up to 4MHz - master to slave phase
shifting capability
• Peak current limiting, hiccup mode short-circuit protection
and over-temperature protection
Applications
• DC/DC POL modules
• µC/µP, FPGA and DSP power
• Plug-in DC/DC modules for routers and switchers
• Portable instruments
• Test and measurement systems
• Li-ion battery powered devices
100
95
3.3VOUT PFM
90
3.3VOUT PWM
85
80
75
70
01 2 3 4 5 6
IOUT (A)
FIGURE 1. EFFICIENCY T = +25°C VIN = 5V
7
8
FN7889 Rev 0.00
September 30, 2015
Page 1 of 21



Renesas ISL8018
ISL8018
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
OUTPUT VOLTAGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL8018IRAJZ
018A
Adjustable
-40 to +85 20 Ld 3x4 QFN
L20.3x4
ISL8018EVAL3Z
Evaluation Board
ISL8018DEMO1Z
Demonstration Board
NOTES:
1. Add “-T” suffix for 6k units or “-T7A” suffix for 250 units Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8018. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL8018
(20 LD QFN)
TOP VIEW
20 19 18 17
PGND 1
16 COMP
PHASE 2
15 SS
PHASE 3
PHASE 4
PAD
14 ISET
13 VSET
VIN 5
12 FS
VIN 6
11 EN
7 8 9 10
FN7889 Rev 0.00
September 30, 2015
Page 2 of 21



Renesas ISL8018
ISL8018
Pin Descriptions
PIN
1, 19, 20
2, 3, 4
5, 6, 7
8
SYMBOL
PGND
PHASE
VIN
PG
9 SYNCOUT
10 SYNCIN
11
12
13
14
15
16, 17
EN
FS
VSET
ISET
SS
COMP, VFB
18 SGND
EPAD
DESCRIPTION
Power ground.
Switching node connection. Connect to one terminal of the inductor.
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.
This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or
SYNCIN. When SYNCOUT voltage reaches 0.8V, a reset circuit will activate and discharge SYNCOUT to
0V. SYNCOUT is held at 0V in PFM light load to reduce quiescent current.
Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state if SYNCIN
is floating.
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the
output capacitor when driven to low.
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for
no margining and connect to VIN for +10%.
ISET is the peak output current limit and skip current limit setting of the regulators. Connect to SGND
for 3A, to VIN for 5A and keep it floating for 8A.
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical
applications, an external compensation network may offer improved performance for some designs.
In addition to regulation, VFB is also used to determine the state of PG.
Signal ground.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.
FN7889 Rev 0.00
September 30, 2015
Page 3 of 21







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)