ANALOG-TO-DIGITAL CONVERTER. ADS824 Datasheet

ADS824 CONVERTER. Datasheet pdf. Equivalent

ADS824 Datasheet
Recommendation ADS824 Datasheet
Part ADS824
Description 10-Bit/ 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER
Feature ADS824; ® ADS 824 E ADS824 10-Bit, 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES q q q q q q q q.
Manufacture Burr-Brown Corporation
Datasheet
Download ADS824 Datasheet




Burr-Brown Corporation ADS824
®
ADS824E
ADS824
TM 10-Bit, 70MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q HIGH SNR: 59dB
q HIGH SFDR: 70dB
q LOW POWER: 315mW
q INTERNAL/EXTERNAL REFERENCE
OPTION
q SINGLE-ENDED OR DIFFERENTIAL
ANALOG INPUT
q PROGRAMMABLE INPUT RANGE:
1Vp-p or 2Vp-p
q LOW DNL: 0.3LSB
q SINGLE +5V SUPPLY OPERATION
q +3V DIGITAL OUTPUT CAPABILITY
q POWER DOWN: 20mW
q 28-LEAD SSOP PACKAGE
APPLICATIONS
q MEDICAL IMAGING
q HDTV VIDEO DIGITIZING
q COMMUNICATIONS
q TEST EQUIPMENT
+VS
ADS824
DESCRIPTION
The ADS824 is a pipeline, CMOS analog-to-digital converter
that operates from a single +5V power supply. This converter
provides excellent performance with a single-ended input and
can be operated with a differential input for added spurious
performance. This high performance converter includes a 10-bit
quantizer, high bandwidth track/hold, and a high accuracy
internal reference. It also allows for the user to disable the
internal reference and utilize external references. This external
reference option provides excellent gain and offset matching
when used in multi-channel applications or in applications
where full scale range adjustment is required.
The ADS824 employs digital error correction techniques to
provide excellent differential linearity for demanding imaging
applications. Its low distortion and high SNR give the extra
margin needed for medical imaging, communications, video,
and test instrumentation. The ADS824 offers power dissipa-
tion of 315mW and also provides a power-down mode, thus
reducing power dissipation to only 20mW.
The ADS824 is specified at a maximum sampling frequency of
70MHz and a single-ended input range of 1.5V to 3.5V. The
ADS824 is available in a 28-lead SSOP package and is pin
compatible with the 10-bit, 40MHz ADS822 and the 10-bit,
60MHz ADS823.
CLK
VDRV
Timing
Circuitry
VIN IN
IN T/H
10-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•••
D9
CM Internal
Reference
Optional External
Reference
Int/Ext
PD OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-1403C
Printed in U.S.A. April, 1999



Burr-Brown Corporation ADS824
SPECIFICATIONS
At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 70MHz, external reference, unless otherwise noted.
ADS824E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
SPECIFIED TEMPERATURE RANGE
Ambient Air
ANALOG INPUT
Standard Single-Ended Input Range
Optional Single-Ended Input Range
Common-Mode Voltage
Optional Differential Input Range
Analog Input Bias Current
Input Impedance
Track-Mode Input Bandwidth
2Vp-p
1Vp-p
2Vp-p
–3dBFS
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious Free Dynamic Range(1)
f = 1MHz
f = 10MHz
Two-Tone Intermodulation Distortion(3)
f = 4.5MHz and 5.5MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz
f = 10MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
f = 10MHz
Effective Number of Bits(4), f = 1MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
Full-Scale Step Acquisition Time
Referred to Full Scale
Referred to Full Scale
Referred to Full Scale
Input Grounded
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current(5) (VIN = 5V)
Low Level Input Current (VIN = 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
Start Conversion
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (IOL = 50µA)
Low Output Voltage, (IOL = 1.6mA)
High Output Voltage, (IOH = 50µA)
High Output Voltage, (IOH = 0.5mA)
Low Output Voltage, (IOL = 50µA)
High Output Voltage, (IOH = 50µA)
3-State Enable Time
3-State Disable Time
Output Capacitance
VDRV = 5V
VDRV = 3V
OE = L
OE = H
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (Referred to –FS)
at 25°C
Zero Error Drift (Referred to –FS)
Gain Error(6)
at 25°C
Gain Error Drift(6)
Gain Error(7)
at 25°C
Gain Error Drift(7)
Power Supply Rejection of Gain
REFT Tolerance
VS = ±5%
Deviation from Ideal 3.5V
REFB Tolerance
Deviation From Ideal 1.5V
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
10 Guaranteed
–40 to +85
1.5 3.5
23
2.5
23
1
1.25 || 5
300
10k 70M
5
Bits
°C
V
V
V
V
µA
M|| pF
MHz
Samples/s
Clk Cyc
±0.3
±0.3
Guaranteed
±0.5
±1.0
±3.0
70
60 68
–63.4
59
55 59
58
50 58
9.3
0.2
3
1.2
2
5
CMOS-Compatible
Rising Edge of Convert Clock
100
10
+3.5
+1.0
5
+4.9
+4.8
+2.8
CMOS-Compatible
Straight Offset Binary
+0.1
+0.2
+0.1
20 40
2 10
5
REFB + 0.8
1.25
±0.5
12
±1.5
38
±0.75
20
68
±10
±10
3.5
1.5
1.6
±3.0
±2.5
±1.5
±25
±25
VS – 1.25
REFT – 0.8
LSB
LSB
LSBs
dBFS(2)
dBFS
dBc
dB
dB
dB
dB
Bits
LSBs rms
ns
ps rms
ns
ns
µA
µA
V
V
pF
V
V
V
V
V
V
ns
ns
pF
%FS
ppm/°C
%FS
ppm/°C
%FS
ppm/°C
dB
mV
mV
V
V
k
®
ADS824
2



Burr-Brown Corporation ADS824
SPECIFICATIONS (CONT)
At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 70MHz, external reference, unless otherwise noted.
ADS824E
PARAMETER
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Output Driver Supply Current (VDRV)
Power Dissipation: VDRV = 5V
VDRV = 3V
VDRV = 5V
VDRV = 3V
Power Down
Thermal Resistance, θJA
28-Lead SSOP
CONDITIONS
Operating
Operating
External Reference
External Reference
Internal Reference
Internal Reference
Operating
MIN
+4.75
TYP
+5.0
66
9
330
315
345
335
20
89
MAX
+5.25
375
UNITS
V
mA
mA
mW
mW
mW
mW
mW
°C/W
NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone
intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental
envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) A 50kpull-down resistor is inserted internally. (6) Includes internal
reference. (7) Excludes internal reference.
PIN CONFIGURATION
Top View
SSOP
GND 1
Bit 1 (MSB) 2
Bit 2 3
Bit 3 4
Bit 4 5
Bit 5 6
Bit 6 7
Bit 7 8
Bit 8 9
Bit 9 10
Bit 10 (LSB) 11
OE 12
PD 13
CLK 14
ADS824
28 VDRV
27 +VS
26 GND
25 IN
24 IN
23 CM
22 REFT
21 ByT
20 ByB
19 REFB
18 INT/EXT
17 RSEL
16 GND
15 +VS
PIN DESCRIPTIONS
PIN DESIGNATOR DESCRIPTION
1
GND
Ground
2
Bit 1
Data Bit 1 (D9) (MSB)
3
Bit 2
Data Bit 2 (D8)
4
Bit 3
Data Bit 3 (D7)
5
Bit 4
Data Bit 4 (D6)
6
Bit 5
Data Bit 5 (D5)
7
Bit 6
Data Bit 6 (D4)
8
Bit 7
Data Bit 7 (D3)
9
Bit 8
Data Bit 8 (D2)
10
Bit 9
Data Bit 9 (D1)
11
Bit 10
Data Bit 10 (D0) (LSB)
12 OE Output Enable. HI = high impedance state.
LO = normal operation (internal pull-
down resistor)
13 PD Power Down. HI = power down; LO = normal
14
CLK
Convert Clock Input
15 +VS +5V Supply
16
GND
Ground
17
RSEL
Input Range Select. HI = 2Vp-p; LO = 1Vp-p
18
INT/EXT
Reference Select. HI = external; LO = internal
19
REFB
Bottom Reference
20 ByB Bottom Ladder Bypass
21 ByT Top Ladder Bypass
22
REFT
Top Reference
23 CM Common-Mode Voltage Output
24 IN Complementary Input (–)
25 IN Analog Input (+)
26
GND
Ground
27 +VS +5V Supply
28
VDRV
Output Logic Driver Supply Voltage
®
3 ADS824







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