ANALOG-TO-DIGITAL CONVERTERS. ADS825 Datasheet

ADS825 CONVERTERS. Datasheet pdf. Equivalent

ADS825 Datasheet
Recommendation ADS825 Datasheet
Part ADS825
Description 10-Bit/ 40MHz Sampling ANALOG-TO-DIGITAL CONVERTERS
Feature ADS825; ® ADS ADS 825 822 ADS822 ADS825 For most current data sheet and other product information, visit .
Manufacture Burr-Brown Corporation
Datasheet
Download ADS825 Datasheet




Burr-Brown Corporation ADS825
®
ADS825
ADS822
ADS822
ADS825
For most current data sheet and other product
information, visit www.burr-brown.com
TM 10-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTERS
FEATURES
q HIGH SNR: 60dB
q HIGH SFDR: 72dBFS
q LOW POWER: 190mW
q INTERNAL/EXTERNAL REFERENCE OPTION
q SINGLE-ENDED OR
FULLY DIFFERENTIAL ANALOG INPUT
q PROGRAMMABLE INPUT RANGE
q LOW DNL: 0.5LSB
q SINGLE +5V SUPPLY OPERATION
q +3V OR +5V LOGIC I/O COMPATIBLE (ADS825)
q POWER DOWN: 20mW
q 28-LEAD SSOP PACKAGE
APPLICATIONS
q MEDICAL IMAGING
q TEST EQUIPMENT
q COMPUTER SCANNERS
q COMMUNICATIONS
q VIDEO DIGITIZING
DESCRIPTION
The ADS822 and ADS825 are pipeline, CMOS analog-to-digital
converters that operate from a single +5V power supply. These
converters provide excellent performance with a single-ended
input and can be operated with a differential input for added
spurious performance. These high-performance converters in-
clude a 10-bit quantizer, high-bandwidth track-and-hold, and a
high-accuracy internal reference. They also allow for the user to
disable the internal reference and utilize external references. This
external reference option provides excellent gain and offset
matching when used in multi-channel applications or in applica-
tions where full-scale range adjustment is required.
The ADS822 and ADS825 employ digital error correction tech-
niques to provide excellent differential linearity for demanding
imaging applications. Its low distortion and high SNR give the
extra margin needed for medical imaging, communications,
video, and test instrumentation. The ADS822 and ADS825 offer
power dissipation of 190mW and also provide a power-down
mode, thus reducing power dissipation to only 20mW. The
ADS825 is +3V or +5V Logic I/O compatible.
The ADS822 and ADS825 are specified at a maximum sampling
frequency of 40MHz and a single-ended input range of 1.5V to
3.5V. The ADS822 and ADS825 are available in a 28-lead SSOP
package and are pin-for-pin compatible with the 10-bit, 60MHz
ADS823 and ADS826, and the 10-bit, 70MHz ADS824, provid-
ing an upgrade path to higher sampling frequencies.
+VS CLK VDRV
ADS822
ADS825
Timing
Circuitry
VIN IN
IN T/H
10-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•••
D9
CM Internal
Reference
Optional External
Reference
Int/Ext
PD OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-1385E
Printed in U.S.A. October, 1999



Burr-Brown Corporation ADS825
SPECIFICATIONS
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
PARAMETER
CONDITIONS
ADS822E
MIN TYP
MAX
ADS825E(1)
MIN TYP MAX
UNITS
RESOLUTION
SPECIFIED TEMPERATURE RANGE
Ambient Air
ANALOG INPUT
Standard Single-Ended Input Range
Optional Single-Ended Input Range
Common-Mode Range
Optional Differential Input Range
Analog Input Bias Current
Input Impedance
Track-Mode Input Bandwidth
2Vp-p
1Vp-p
2Vp-p
–3dBFS Input
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious Free Dynamic Range(2)
f = 1MHz
f = 10MHz
Two-Tone Intermodulation Distortion(4)
f = 9.5MHz and 9.9MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz
f = 10MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
f = 10MHz
Effective Number of Bits(5), f = 1MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
Full-Scale Step Acquisition Time
Referred to Full Scale
Referred to Full Scale
Referred to Full Scale
Input Tied to Common-Mode
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current(6) (VIN = 5VDD)
Low Level Input Current (VIN = 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
Start Conversion
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (IOL = 50µA to 1.6mA)
High Output Voltage, (IOH = 50µA to 0.5mA)
Low Output Voltage, (IOL = 50µA to 1.6mA)
High Output Voltage, (IOH = 50µA to 0.5mA)
3-State Enable Time
3-State Disable Time
Output Capacitance
VDRV = 5V
VDRV = 3V
OE = H to L
OE = L to H
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (referred to –FS)
at 25°C
Zero Error Drift (referred to –FS)
Midscale Offset Error
at 25°C
Gain Error(7)
at 25°C
Gain Error Drift(7)
Gain Error(8)
at 25°C
Gain Error Drift(8)
Power Supply Rejection of Gain
REFT Tolerance
VS = ±5%
Deviation From Ideal 3.5V
REFB Tolerance
Deviation From Ideal 1.5V
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
REFT to REFB
10 Guaranteed
–40 to +85
1.5
2
2.5
2
1
1.25 || 5
300
3.5
3
3
10k
5
40M
10 Guaranteed
–40 to +85
TT
TT
T
TT
T
T
T
TT
T
Bits
°C
V
V
V
V
µA
M|| pF
MHz
Samples/s
Clk Cyc
±0.25
±0.5
Guaranteed
±0.5
±1.0
±2.0
72
63 66
–67
60
57 60
59
56 58
9.5
0.2
3
1.2
2
5
T
T
Guaranteed
T
T
T
71
60 65
T
T
TT
T
TT
T
T
T
T
T
T
LSB
LSB
LSBs
dBFS(3)
dBFS
dBc
dB
dB
dB
dB
Bits
LSBs rms
ns
ps rms
ns
ns
CMOS-Compatible
Rising Edge of Convert Clock
100
10
+3.5
+1.0
5
TTL, +3V/+5V CMOS-Compatible
Rising Edge of Convert Clock
T
T
+2.0
+0.8
T
µA
µA
V
V
pF
CMOS-Compatible
Straight Offset Binary
+0.1
+4.9
+0.1
+2.8
2 40
2 10
5
CMOS-Compatible
Straight Offset Binary
T
T
T
T
TT
TT
T
V
V
V
V
ns
ns
pF
±1.0
5
REFB + 0.8
1.25
±1.5
38
±0.75
25
70
±10
±10
3.5
1.5
1.6
±3.0
±2.5
±1.5
±25
±25
VS – 1.25
REFT – 0.8
T
T
T
T
±0.29
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
% FS
ppm/°C
% FS
% FS
ppm/°C
% FS
ppm/°C
dB
mV
mV
V
V
k
®
ADS822, ADS825
2



Burr-Brown Corporation ADS825
SPECIFICATIONS (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
PARAMETER
CONDITIONS
ADS822E
MIN TYP
MAX
ADS825E(1)
MIN TYP MAX
UNITS
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation: VDRV = 5V
VDRV = 3V
VDRV = 5V
VDRV = 3V
Power Down
Thermal Resistance, θJA
28-Lead SSOP
Operating
Operating (External Reference)
External Reference
External Reference
Internal Reference
Internal Reference
Operating
+4.75
+5.0
+5.25
T
T
T
40 T
200 230
TT
190 T
250 T
240 T
20 T
89 T
V
mA
mW
mW
mW
mW
mW
°C/W
T Indicates the same specifications as the ADS822E.
NOTES: (1) ADS825E accepts a +3V clock input. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to Full Scale. (4) Two-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined
by (SINAD – 1.76)/6.02. (6) A 50kpull-down resistor is inserted internally on OE pin. (7) Includes internal reference. (8) Excludes internal reference.
PIN CONFIGURATION
Top View
SSOP
GND 1
Bit 1 (MSB) 2
Bit 2 3
Bit 3 4
Bit 4 5
Bit 5 6
Bit 6 7
Bit 7 8
Bit 8 9
Bit 9 10
Bit 10 (LSB) 11
OE 12
PD 13
CLK 14
ADS822
ADS825
28 VDRV
27 +VS
26 GND
25 IN
24 IN
23 CM
22 REFT
21 ByT
20 ByB
19 REFB
18 INT/EXT
17 RSEL
16 GND
15 +VS
PIN DESCRIPTIONS
PIN DESIGNATOR DESCRIPTION
1
GND
Ground
2
Bit 1
Data Bit 1 (D9) (MSB)
3
Bit 2
Data Bit 2 (D8)
4
Bit 3
Data Bit 3 (D7)
5
Bit 4
Data Bit 4 (D6)
6
Bit 5
Data Bit 5 (D5)
7
Bit 6
Data Bit 6 (D4)
8
Bit 7
Data Bit 7 (D3)
9
Bit 8
Data Bit 8 (D2)
10
Bit 9
Data Bit 9 (D1)
11
Bit 10
Data Bit 10 (D0) (LSB)
12 OE Output Enable. HI = high impedance state
LO = normal operation (internal pull-down
resistor)
13 PD Power Down. HI = enable; LO = disable
14
CLK
Convert Clock Input
15 +VS +5V Supply
16
GND
Ground
17
RSEL
Input Range Select. HI = 2V; LO = 1V
18
INT/EXT
Reference Select. HI = external, LO = internal
19
REFB
Bottom Reference
20 ByB Bottom Ladder Bypass
21 ByT Top Ladder Bypass
22
REFT
Top Reference
23 CM Common-Mode Voltage Output
24 IN Complementary Input (–)
25 IN Analog Input (+)
26
GND
Analog Ground
27 +VS +5V Supply
28
VDRV
Output Logic Driver Supply Voltage
®
3 ADS822, ADS825







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