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Type-C Hub. CYUSB3343 Datasheet

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Type-C Hub. CYUSB3343 Datasheet






CYUSB3343 Hub. Datasheet pdf. Equivalent




CYUSB3343 Hub. Datasheet pdf. Equivalent





Part

CYUSB3343

Description

HX3C USB Type-C Hub



Feature


CYUSB3333 CYUSB3343 HX3C USB Type-C Hub with PD HX3C USB Type-C Hub with PD Fu nctional Description HX3C is a family of USB 3.1 Gen 1 Type-C hub with USB Po wer Delivery (PD) that complies with th e USB 3.1 Gen 1 specification, and the latest Type-C and PD standards. HX3C su pports SuperSpeed (SS), Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on all the ports. HX3.
Manufacture

Cypress Semiconductor

Datasheet
Download CYUSB3343 Datasheet


Cypress Semiconductor CYUSB3343

CYUSB3343; C provides a complete Type-C and USB PD port controller solution in Upstream (U S) and one Downstream (DS) port. Featur es ■ USB 3.1 Gen 1-compliant Hub Con troller ❐ All ports support SS (5 Gbp s), and are backward-compatible with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) ❐ SS and USB 2.0 Link Power Man agement (LPM) ❐ Dedicated Hi-Speed Tr ansaction Translators (Mul.


Cypress Semiconductor CYUSB3343

ti-TT) ❐ Configurable USB SS and USB 2 .0 PHY. ■ Integrated Type-C transceiv er, supporting two Type-C ports ❐ Typ e-C supported in two ports (1 US port a nd 1 DS port) ❐ Integrated transceive r (baseband PHY) ❐ Integrated UFP (RD ), and current so .


Cypress Semiconductor CYUSB3343

.

Part

CYUSB3343

Description

HX3C USB Type-C Hub



Feature


CYUSB3333 CYUSB3343 HX3C USB Type-C Hub with PD HX3C USB Type-C Hub with PD Fu nctional Description HX3C is a family of USB 3.1 Gen 1 Type-C hub with USB Po wer Delivery (PD) that complies with th e USB 3.1 Gen 1 specification, and the latest Type-C and PD standards. HX3C su pports SuperSpeed (SS), Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on all the ports. HX3.
Manufacture

Cypress Semiconductor

Datasheet
Download CYUSB3343 Datasheet




 CYUSB3343
CYUSB3333
CYUSB3343
HX3C USB Type-C Hub with PD
HX3C USB Type-C Hub with PD
Functional Description
HX3C is a family of USB 3.1 Gen 1 Type-C hub with USB Power Delivery (PD) that complies with the USB 3.1 Gen 1 specification,
and the latest Type-C and PD standards. HX3C supports SuperSpeed (SS), Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS)
on all the ports. HX3C provides a complete Type-C and USB PD port controller solution in Upstream (US) and one Downstream (DS)
port.
Features
USB 3.1 Gen 1-compliant Hub Controller
All ports support SS (5 Gbps), and are backward-compatible
with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps)
SS and USB 2.0 Link Power Management (LPM)
Dedicated Hi-Speed Transaction Translators (Multi-TT)
Configurable USB SS and USB 2.0 PHY.
Integrated Type-C transceiver, supporting two Type-C ports
Type-C supported in two ports (1 US port and 1 DS port)
Integrated transceiver (baseband PHY)
Integrated UFP (RD), and current sources for DFP (RP)
Upstream: Type-C or Type-B port
Downstream: One Type-C and 2 Type-A or 3 Type-A ports
Block Diagram
Integrated DFP (RP), UFP (RD) termination resistors
Charging Standard support:
USB Power Delivery (PD) 2.0, Battery Charging v1.2 Apple
Charging Standard
PD policy engine configures power profiles dynamically
Ghost Charge™: Charging DS without US connection
Firmware upgradable over USB
System-level ESD protection on CC pins: 8-kV contact, 15-kV
Air Gap IEC61000-4-2 level 4C
121-ball BGA (10 mm × 10 mm, 0.8-mm ball-pitch)
UPSTREAM PORT
USB2.0  USB3.0 VBUS
PHY PHY DETECT
TYPE-C PD
CONTROLLER
PHY INTERFACE
HUB CONTROLLER
REPEATER
TRANSACTION
TRANSLATORS
UPSTREAM PORT CONTROL
ROUTING
HUB CONTROLLER
UPSTREAM
BUFFERS
DOWNSTREAM
BUFFERS
USB 2.0 Specific
USB 3.0 (SS) Specific
CPU
RAM ROM
I2C I/Fs
PLL
CC1_P1
CC2_P1
3.3V
1.2V
I2C_SDAx
I2C_SCLx
26
MHz
ROUTING LOGIC
BUFFER AND ROUTING LOGIC
TYPE-C PD
CONTROLLER
CC1_P2
CC2_P2
USB 2.0 USB 3.0 PORT
PHY
PHY CONTROL
USB 2.0 USB 3.0 PORT
PHY
PHY CONTROL
USB 2.0
USB
PHY BILLBOARD
USB 2.0 USB 3.0 PORT
PHY
PHY CONTROL
PORT1
PORT2
PORT3
PORT4
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-10462 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 16, 2017




 CYUSB3343
CYUSB3333
CYUSB3343
Contents
Architecture Overview ..................................................... 3
USB-PD Controller ...................................................... 3
SS Hub Controller ....................................................... 3
USB 2.0 Hub Controller ............................................... 3
USB Billboard .............................................................. 3
CPU ............................................................................. 3
Flash ............................................................................ 3
I2C Interfaces .............................................................. 3
Port Controller ............................................................. 3
Applications ...................................................................... 4
HX3C Product Options ..................................................... 4
Product Features .............................................................. 5
Ghost Charge in Type-A DS Port ................................ 5
Vendor-Command Support ......................................... 5
Pin Information ................................................................. 6
Pin Description ................................................................. 7
System Interfaces ........................................................... 10
Upstream Port (US) ................................................... 10
Downstream Ports (DS1, 2, 3, 4) .............................. 10
Communication Interfaces (I2C) ................................ 10
Oscillator ................................................................... 10
Power Control ............................................................ 10
Reset ......................................................................... 10
Hub Configuration Mode Select ................................ 10
Hub Configuration Options ........................................ 11
EMI ................................................................................... 15
ESD .................................................................................. 15
Absolute Maximum Ratings .......................................... 16
Electrical Specifications ................................................ 16
DC Electrical Characteristics ..................................... 16
Power Consumption .................................................. 18
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Packaging ........................................................................ 20
Package Diagram ............................................................ 21
Acronyms ........................................................................ 22
Reference Documents .................................................... 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Document History ........................................................... 23
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Document Number: 002-10462 Rev. *C
Page 2 of 24




 CYUSB3343
CYUSB3333
CYUSB3343
Architecture Overview
The Block Diagram on page 1 shows the HX3C architecture.
HX3C consists of two independent hub controllers (SS and USB
2.0), the Cortex-M0 CPU subsystem, two USB Type-C PD
controllers, USB billboard, I2C interface, and port controller
blocks.
USB-PD Controller
HX3C has two USB-PD controllers consisting of a USB Type-C
baseband transceiver and physical-layer logic. This transceiver
performs the BMC and the 4b/5b encoding and decoding
functions as well as the 1.2-V front end. These controllers
integrate the required termination resistors to identify the role of
the EZ-PD solutions on two Type-C ports of the HX3C device.
RD is used to identify a UFP in a dock or a dongle. When
configured as a DFP, integrated current sources perform the role
of RP or pull-up resistors. These current sources can be
programmed to indicate the complete range of current capacity
on VBUS defined in the Type-C spec. HX3C PD ports respond
to all USB-PD communication.
The USB-PD controller contains a 8-bit Successive Approxi-
mation Register (SAR) ADC for analog-to-digital conversions
(ADC). The ADC includes a 8-bit DAC and a comparator. The
DAC output forms the positive input of the comparator. The
negative input of the comparator is from a 4-input multiplexer.
The four inputs of the multiplexer are a pair of global analog
multiplex busses an internal bandgap voltage and an internal
voltage proportional to the absolute temperature. All GPIO inputs
can be connected to the global Analog Multiplex Busses through
a switch at each GPIO that can enable that GPIO to be
connected to the mux bus for ADC use. The CC1, and CC2 pins
are not available to connect to the mux busses.
SS Hub Controller
This block supports the SS hub functionality based on the
USB 3.1 Gen 1 specification. The SS hub controller supports the
following:
SS link power management (U0, U1, U2, U3 states)
Full-duplex data transmission
USB 2.0 Hub Controller
This block supports the LS, FS, and HS hub functionalities. It
includes the repeater, frame timer, and four transaction trans-
lators.
The USB 2.0 hub controller block supports the following:
USB 2.0 link power management (L0, L1, L2, L3 states)
Suspend, resume, and remote wake-up signaling
Multi-TT (one TT for each DS port)
USB Billboard
HX3C has integrated USB Billboard controller. This is USB 2.0
certified Full-Speed (12 Mbps) controller, which supports native
Billboard device class driver.
CPU
The Cortex-M0 CPUs in HX3C are part of the 32-bit MCU
controller, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPUs also include a serial wire debug (SWD) interface,
which is a two-wire form of JTAG.
Flash
HX3C has one flash module each for both USB-PD controllers
and one for Billboard; with a flash accelerator, tightly coupled to
the CPU to improve average access times from the flash block.
The flash block is designed to deliver 1 wait-state (WS) access
time at 48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average.
I2C Interfaces
HX3C supports two I2C interfaces, which supports I2C slave,
master and multi-master configurations. One of the I2C inter-
faces is used for configuration of the hub during boot-up. Config-
uration can be from an external I2C EEPROM or from an external
I2C master. Second I2C interface shall be used to configure
external I2C slave device from HX3C.
Port Controller
The port controller block controls the DS port power to comply
with the BC v1.2 and USB 3.1 Gen 1 specifications. Control
signals for external power switches are implemented within the
chip. HX3C controls the external power switches at power-on to
reduce in-rush current.
Document Number: 002-10462 Rev. *C
Page 3 of 24



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