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Static RAM. CY7C026AV Datasheet

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Static RAM. CY7C026AV Datasheet






CY7C026AV RAM. Datasheet pdf. Equivalent




CY7C026AV RAM. Datasheet pdf. Equivalent





Part

CY7C026AV

Description

Dual-Port Static RAM



Feature


CY7C024AV CY7C025AV CY7C026AV 3.3 V, 4K/ 8K/16K × 16 Dual-Port Static RAM 3.3 V, 4K/8K/16K × 16 Dual-Port Static RAM Features ■ True dual-ported memory c ells which enable simultaneous access o f the same memory location ■ 4, 8 or 16K × 16 organization (CY7C024AV/025AV /026AV) ■ 0.35 micron CMOS for optimu m speed and power ■ High speed access : 20 ns and 25 ns ■ Low opera.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C026AV Datasheet


Cypress Semiconductor CY7C026AV

CY7C026AV; ting power ❐ Active: ICC = 115 mA (typ ical) ❐ Standby: ISB3 = 10 A (typi cal) ■ Fully asynchronous operation Automatic power down ■ Expandable data bus to 32 bits or more using Maste r and Slave chip select when using more than one device ■ On chip arbitratio n logic ■ Semaphores included to perm it software handshaking between ports ■ INT flag for port-to-port commun.


Cypress Semiconductor CY7C026AV

ication ■ Separate upper byte and lowe r byte control ■ Pin select for Maste r or Slave (M/S) ■ Commercial and ind ustrial temperature ranges ■ Availabl e in 100-pin Pb-free TQFP and 100-pin T QFP Functional Description The CY .


Cypress Semiconductor CY7C026AV

.

Part

CY7C026AV

Description

Dual-Port Static RAM



Feature


CY7C024AV CY7C025AV CY7C026AV 3.3 V, 4K/ 8K/16K × 16 Dual-Port Static RAM 3.3 V, 4K/8K/16K × 16 Dual-Port Static RAM Features ■ True dual-ported memory c ells which enable simultaneous access o f the same memory location ■ 4, 8 or 16K × 16 organization (CY7C024AV/025AV /026AV) ■ 0.35 micron CMOS for optimu m speed and power ■ High speed access : 20 ns and 25 ns ■ Low opera.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C026AV Datasheet




 CY7C026AV
CY7C024AV
CY7C025AV
CY7C026AV
3.3 V, 4K/8K/16K × 16 Dual-Port
Static RAM
3.3 V, 4K/8K/16K × 16 Dual-Port Static RAM
Features
True dual-ported memory cells which enable simultaneous
access of the same memory location
4, 8 or 16K × 16 organization
(CY7C024AV/025AV/026AV)
0.35 micron CMOS for optimum speed and power
High speed access: 20 ns and 25 ns
Low operating power
Active: ICC = 115 mA (typical)
Standby: ISB3 = 10 A (typical)
Fully asynchronous operation
Automatic power down
Expandable data bus to 32 bits or more using Master and Slave
chip select when using more than one device
On chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Separate upper byte and lower byte control
Pin select for Master or Slave (M/S)
Commercial and industrial temperature ranges
Available in 100-pin Pb-free TQFP and 100-pin TQFP
Functional Description
The CY7C024AV/025AV/026AV consist of an array of 4K, 8K, and
16K words of 16 bits each of dual-port RAM cells, IO and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory.
To handle simultaneous writes and reads to the same location, a
BUSY pin is provided on each port. Two Interrupt (INT) pins can be
used for port to port communication. Two Semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin, the
devices can function as a master (BUSY pins are outputs) or as a
slave (BUSY pins are inputs). They also have an automatic power
down feature controlled by CE. Each port has its own output enable
control (OE), which enables data to be read from the device.
For a complete list of related resources, click here.
Selection Guide
Parameter
Maximum Access Time
Typical Operating Current
Typical Standby Current for ISB1
(Both ports TTL Level)
Typical Standby Current for ISB3
(Both ports CMOS Level)
CY7C024AV/025AV/026AV
-20
20
120
35
10
CY7C024AV/025AV/026AV
-25
25
115
30
10
Unit
ns
mA
mA
A
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06052 Rev. *T
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 1, 2017




 CY7C026AV
CY7C024AV
CY7C025AV
CY7C026AV
Logic Block Diagram
R/WL
UBL
CEL
LBL
OEL
IO8L–IO15L[1]
IO0L–IO7[L2]
8
8
IO
Control
IO
Control
R/WR
UBR
CER
LBR
OER
8 [1]
8 IO8L– IO[215] R
IO0L– IO7R
A0L–A[131]/1213L
[3]
A0L–A11/12/13L
CEL
OEL
R/WL
SEML [4]
BUSYL
INTL
UBL
LBL
12/13/14 Address
Decode
12/13/14
True Dual-Ported
RAM Array
Interrupt
Semaphore
Arbitration
M/S
Address 12/13/14
Decode
12/13/14
A0R–A[131]/12/13R
[3]
A0R–A11/12/13R
CER
OER
R/WR
[4] SEMR
BUSYR
INTR
UBR
LBR
Notes
1. IO8–IO15 for × 16 devices
2. IO0–IO7 for × 16 devices
3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
4. BUSY is an output in master mode and an input in slave mode.
Document Number: 38-06052 Rev. *T
Page 2 of 24




 CY7C026AV
CY7C024AV
CY7C025AV
CY7C026AV
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Write Operation ........................................................... 6
Read Operation ........................................................... 7
Interrupts ..................................................................... 7
Busy ............................................................................ 7
Master/Slave ............................................................... 7
Semaphore Operation ................................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
AC Test Loads and Waveforms ..................................... 10
Data Retention Mode ...................................................... 10
Timing .............................................................................. 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 19
4K × 16 3.3 V Asynchronous Dual-Port SRAM ......... 19
8K × 16 3.3 V Asynchronous Dual-Port SRAM ......... 19
16K × 16 3.3 V Asynchronous Dual-Port SRAM ....... 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Document Number: 38-06052 Rev. *T
Page 3 of 24



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