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802.11n/ac MAC/Baseband/Radio. CYW43455 Datasheet

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802.11n/ac MAC/Baseband/Radio. CYW43455 Datasheet






CYW43455 MAC/Baseband/Radio. Datasheet pdf. Equivalent




CYW43455 MAC/Baseband/Radio. Datasheet pdf. Equivalent





Part

CYW43455

Description

Single-Chip 5G WiFi IEEE 802.11n/ac MAC/Baseband/Radio



Feature


CYW43455 Single-Chip 5G WiFi IEEE 802.11 n/ac MAC/ Baseband/ Radio with Integrat ed Bluetooth 5.0 The Cypress CYW43455 single-chip device provides the highest level of integration for Internet of T hings applications and handheld wireles s system with integrated single-stream IEEE 802.11ac MAC/baseband/radio and, B luetooth 5.0. In IEEE 802.11ac mode, th e WLAN operation s.
Manufacture

Cypress Semiconductor

Datasheet
Download CYW43455 Datasheet


Cypress Semiconductor CYW43455

CYW43455; upports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz chan nels for data rates of up to 433.3 Mbps . All rates specified in the IEEE 802.1 1a/b/g/n are supported. Included on-chi p are 2.4 GHz and 5 GHz transmit amplif iers and receive low-noise amplifiers. Optional external PAs and LNAs are also supported. The WLAN section supports t he following host in.


Cypress Semiconductor CYW43455

terface options: an SDIO v3.0 interface that can operate in 4b or 1b mode, a hi gh-speed 4-wire UART, and a PCIe1Gen1 ( 3.0 compliant) interface. The Bluetooth section supports a high-speed 4-wire U ART interface. Using advanced design te chniques and process te .


Cypress Semiconductor CYW43455

.

Part

CYW43455

Description

Single-Chip 5G WiFi IEEE 802.11n/ac MAC/Baseband/Radio



Feature


CYW43455 Single-Chip 5G WiFi IEEE 802.11 n/ac MAC/ Baseband/ Radio with Integrat ed Bluetooth 5.0 The Cypress CYW43455 single-chip device provides the highest level of integration for Internet of T hings applications and handheld wireles s system with integrated single-stream IEEE 802.11ac MAC/baseband/radio and, B luetooth 5.0. In IEEE 802.11ac mode, th e WLAN operation s.
Manufacture

Cypress Semiconductor

Datasheet
Download CYW43455 Datasheet




 CYW43455
CYW43455
Single-Chip 5G WiFi IEEE 802.11n/ac MAC/
Baseband/ Radio with Integrated Bluetooth 5.0
The Cypress CYW43455 single-chip device provides the highest level of integration for Internet of Things applications and handheld
wireless system with integrated single-stream IEEE 802.11ac MAC/baseband/radio and, Bluetooth 5.0.
In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz
channels for data rates of up to 433.3 Mbps. All rates specified in the IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz
and 5 GHz transmit amplifiers and receive low-noise amplifiers. Optional external PAs and LNAs are also supported.
The WLAN section supports the following host interface options: an SDIO v3.0 interface that can operate in 4b or 1b mode, a
high-speed 4-wire UART, and a PCIe1Gen1 (3.0 compliant) interface. The Bluetooth section supports a high-speed 4-wire UART
interface.
Using advanced design techniques and process technology to reduce active and idle power, the CYW43455 is designed to address
the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which
simplifies the system power topology and allows for direct operation from a mobile platform battery while maximizing battery life.
The CYW43455 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which
ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external
radios (such as LTE cellular and GPS) is provided via an external interface. As a result, enhanced overall quality for simultaneous
voice, video, and data transmission on a handheld system is achieved.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
BCM43455
BCM43455XKUBG
BCM43455HKUBG
BCM4329
BCM4330
CYW43455
CYW43455XKUBG
CYW43455HKUBG
CYW4329
CYW4330
Cypress Part Number
Features
IEEE 802.11x Key Features
IEEE 802.11ac compliant.
Support for TurboQAM® (MCS0–MCS8 86 Mbps and MCS0–
MCS9 96 Mbps) HT20, 20 MHz channel bandwidth.
Single-stream spatial multiplexing up to 433.3 Mbps data rate.
Supports 20, 40, and 80 MHz channels with optional SGI (256
QAM modulation).
Full IEEE 802.11a/b/g/n legacy compatibility with enhanced
performance.
Supports explicit IEEE 802.11ac transmit beamforming.
TX and RX low-density parity check (LDPC) support for
improved range and power efficiency.
On-chip power amplifiers and low-noise amplifiers for both
bands.
Support for optional front-end modules (FEM) with external PAs
and LNAs.
Supports optional integrated T/R switch for 2.4 GHz band.
Supports RF front-end architecture with a single dual-band
antenna shared between Bluetooth and WLAN for lowest
system cost.
Shared Bluetooth and WLAN receive signal path eliminates the
need for an external power splitter while maintaining excellent
sensitivity for both Bluetooth and WLAN.
Internal fractional-n PLL allows support for a wide range of
reference clock frequencies.
Supports IEEE 802.15.2 external coexistence interface to
optimize bandwidth utilization with other co-located wireless
technologies such as LTE or GPS.
1. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-15051 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 22, 2019




 CYW43455
CYW43455
Supports standard SDIO v3.0 (including DDR50 mode at 50
MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit) interfaces.
Backward compatible with SDIO v2.0 host interfaces.
PCIe2 mode complies with PCI Express base specification
revision 3.0 compliant Gen1 interface for ×1 lane and power
management base specification.
Integrated ARMCR4 processor with tightly coupled memory for
complete WLAN subsystem functionality and minimizing the
need to wake-up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field upgrade with
future features. On-chip memory includes 800KB SRAM and
704 KB ROM.
Bluetooth Key Features
Complies with Bluetooth Core Specification v5.0 with provi-
sions for supporting future specifications.
QDID:121361
Declaration ID: D040197
Bluetooth Class 1 or Class 2 transmitter operation.
Supports extended synchronous connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
Adaptive frequency hopping (AFH) for reducing radio
frequency interference.
Interface support, host controller interface (HCI) using a
high-speed UART interface and PCM for audio data.
Low power consumption improves battery life of handheld
devices.
Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
Automatic frequency detection for standard crystal and TCXO
values.
General Features
Supports battery voltage range from 3.0 V to 5.25 V supplies
with internal switching regulator.
Programmable dynamic power management
6 Kbit OTP for storing board parameters.
GPIOs: 15
140-ball WLBGA package (4.47 mm × 5.27 mm, 0.4 mm pitch).
Security:
WPA and WPA2 (Personal) support for powerful encryption
and authentication
AES and TKIP in hardware for faster data encryption and
IEEE 802.11i compatibility
Reference WLAN subsystem provides Cisco Compatible Ex-
tensions (CCX, CCX 2.0, CCX 3.0, and CCX 4.0)
Reference WLAN subsystem provides Wi-Fi Protected Setup
(WPS)
Worldwide regulatory support: Global products supported with
worldwide homologated design.
Figure 1. Functional Block Diagram
VIO VBAT
WLAN
Host I/F
WL_REG_ON
PCIe2
UART
SDIO
External
Coexistence I/F
COEX
Bluetooth
Host I/F
BT_REG_ON
UART
I2S
PCM
BT_DEV_WAKE
BT_HOST_WAKE
5 GHz WLAN Tx
5 GHz WLAN Rx
FEM or
T/R
S w itc h
CYW43455
2.4 GHz WLAN Tx
2.4 GHz WLAN/BT Rx
Bluetooth Tx
FEM or
O p tio n a l
T/R
Switch
CBF
2. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.
Document Number: 002-15051 Rev. *O
Page 2 of 118




 CYW43455
CYW43455
Contents
1. CYW43455 Overview......................................... 5
1.1 Overview ............................................................. 5
1.2 Standards Compliance ........................................ 6
2. Power Supplies and Power Management ....... 7
2.1 Power Supply Topology ...................................... 7
2.2 CYW43455 PMU Features .................................. 7
2.3 WLAN Power Management ............................... 10
2.4 PMU Sequencing .............................................. 10
2.5 Power-Off Shutdown ......................................... 11
2.6 Power-Up/Power-Down/Reset Circuits ............. 11
3. Frequency References ................................... 12
3.1 Crystal Interface and Clock Generation ............ 12
3.2 External Frequency Reference ......................... 13
3.3 Frequency Selection ......................................... 14
3.4 External 32.768 kHz Low-Power Oscillator ....... 15
4. Bluetooth Subsystem Overview .................... 16
4.1 Features ............................................................ 16
4.2 Bluetooth Radio ................................................. 17
5. Bluetooth Baseband Core.............................. 19
5.1 Bluetooth 4.0 Features ...................................... 19
5.2 Bluetooth 4.2 Features ...................................... 19
5.3 Bluetooth Low Energy ....................................... 19
5.4 Bluetooth 5.0 ..................................................... 19
5.5 Link Control Layer ............................................. 20
5.6 Test Mode Support ............................................ 20
5.7 Bluetooth Power Management Unit .................. 21
5.8 Adaptive Frequency Hopping ............................ 24
5.9 Advanced Bluetooth/WLAN Coexistence .......... 25
5.10 Fast Connection (Interlaced Page and Inquiry
Scans) ............................................................... 25
6. Microprocessor and Memory Unit for
Bluetooth ......................................................... 26
6.1 RAM, ROM, and Patch Memory ........................ 26
6.2 Reset ................................................................. 26
7. Bluetooth Peripheral Transport Unit ............. 27
7.1 SPI Interface ..................................................... 27
7.2 SPI/UART Transport Detection ......................... 27
7.3 PCM Interface ................................................... 27
7.4 UART Interface ................................................. 35
7.5 I2S Interface ...................................................... 36
8. WLAN Global Functions................................. 39
8.1 WLAN CPU and Memory Subsystem ............... 39
Document Number: 002-15051 Rev. *O
8.2 One-Time Programmable Memory .....................39
8.3 GPIO Interface ...................................................39
8.4 External Coexistence Interface ..........................40
8.5 UART Interface ..................................................41
8.6 JTAG/SWD Interface ..........................................41
9. WLAN Host Interfaces .................................... 42
9.1 SDIO v3.0 ...........................................................42
9.2 SDIO Pins ..........................................................42
9.3 PCI Express Interface ........................................44
9.4 Transaction Layer Interface ...............................45
10. Wireless LAN MAC and PHY.......................... 47
10.1 IEEE 802.11ac MAC ..........................................47
10.2 IEEE 802.11ac PHY ...........................................50
11. WLAN Radio Subsystem ............................... 51
11.1 Receiver Path .....................................................51
11.2 Transmit Path .....................................................51
11.3 Calibration ..........................................................51
12. Ball Map and Pin Descriptions ...................... 53
12.1 Ball Map .............................................................53
12.2 Pin List by Pin Number .......................................54
12.3 Pin List by Pin Name ..........................................56
12.4 Pin Descriptions .................................................58
12.5 WLAN GPIO Signals and Strapping Options .....63
12.6 I/O States ...........................................................66
13. DC Characteristics.......................................... 70
13.1 Absolute Maximum Ratings ...............................70
13.2 Environmental Ratings .......................................70
13.3 Electrostatic Discharge Specifications ...............70
13.4 Recommended Operating Conditions and DC
Characteristics ...................................................71
14. Bluetooth RF Specifications .......................... 73
15. WLAN RF Specifications................................ 79
15.1 Introduction ........................................................79
15.2 2.4 GHz Band General RF Specifications ..........79
15.3 WLAN 2.4 GHz Receiver Performance
Specifications .....................................................80
15.4 WLAN 2.4 GHz Transmitter Performance
Specifications .....................................................83
15.5 WLAN 5 GHz Receiver Performance
Specifications .....................................................84
15.6 WLAN 5 GHz Transmitter Performance
Specifications .....................................................88
Page 3 of 118



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