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Programmable System-on-Chip. PSoC61 Datasheet

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Programmable System-on-Chip. PSoC61 Datasheet






PSoC61 System-on-Chip. Datasheet pdf. Equivalent




PSoC61 System-on-Chip. Datasheet pdf. Equivalent





Part

PSoC61

Description

Programmable System-on-Chip



Feature


PSoC® 6 MCU: PSoC 61 Datasheet Programm able System-on-Chip (PSoC®) General D escription PSoC® is a scalable and re configurable platform architecture for a family of programmable embedded syste m controllers with Arm® Cortex® CPUs (single and multi-core). The PSoC 6 pro duct family, based on an ultra low-powe r 40-nm platform, is a combination of a dual-core microcontrol.
Manufacture

Cypress Semiconductor

Datasheet
Download PSoC61 Datasheet


Cypress Semiconductor PSoC61

PSoC61; ler with low-power Flash technology and digital programmable logic, high-perfor mance analog-to-digital and digital-to- analog conversion, low-power comparator s, and standard communication and timin g peripherals. Features 32-bit Dual Co re CPU Subsystem ■ 150-MHz Arm Cortex -M4F CPU with single-cycle multiply (Fl oating Point and Memory Protection Unit ) for user applicati.


Cypress Semiconductor PSoC61

on ■ 100-MHz Cortex M0+ CPU with singl e-cycle multiply and MPU for System fun ctions (not user programmable) ■ User -selectable core logic operation at eit her 1.1 V or 0.9 V ■ Inter-processor communication supported in hardware ■ 8 KB 4-way set-as .


Cypress Semiconductor PSoC61

.

Part

PSoC61

Description

Programmable System-on-Chip



Feature


PSoC® 6 MCU: PSoC 61 Datasheet Programm able System-on-Chip (PSoC®) General D escription PSoC® is a scalable and re configurable platform architecture for a family of programmable embedded syste m controllers with Arm® Cortex® CPUs (single and multi-core). The PSoC 6 pro duct family, based on an ultra low-powe r 40-nm platform, is a combination of a dual-core microcontrol.
Manufacture

Cypress Semiconductor

Datasheet
Download PSoC61 Datasheet




 PSoC61
PSoC® 6 MCU: PSoC 61
Datasheet
Programmable System-on-Chip (PSoC®)
General Description
PSoC® is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with Arm®
Cortex® CPUs (single and multi-core). The PSoC 6 product family, based on an ultra low-power 40-nm platform, is a combination of
a dual-core microcontroller with low-power Flash technology and digital programmable logic, high-performance analog-to-digital and
digital-to-analog conversion, low-power comparators, and standard communication and timing peripherals.
Features
32-bit Dual Core CPU Subsystem
150-MHz Arm Cortex-M4F CPU with single-cycle multiply
(Floating Point and Memory Protection Unit) for user
application
100-MHz Cortex M0+ CPU with single-cycle multiply and MPU
for System functions (not user programmable)
User-selectable core logic operation at either 1.1 V or 0.9 V
Inter-processor communication supported in hardware
8 KB 4-way set-associative Instruction Caches for the M4 and
M0+ CPUs respectively
Active CPU power consumption slope with 1.1-V core operation
for the Cortex M4 is 40 µA/MHz and 20 µA/MHz for the Cortex
M0+, both at 3.3-V chip supply voltage with the internal buck
regulator
Active CPU power consumption slope with 0.9-V core operation
for the Cortex M4 is 22 µA/MHz and 15 µA/MHz for the Cortex
M0+, both at 3.3-V chip supply voltage with the internal buck
regulator
Two DMA controllers with 16 channels each
Flexible Memory Subsystem
1 MB Application Flash with 32 KB EEPROM area and 32 KB
Secure Flash
128-bit wide Flash accesses reduce power
SRAM with Selectable Retention Granularity
288 KB integrated SRAM
32 KB retention boundaries (can retain 32 KB to 288 KB in 32
KB increments)
OTP E-Fuse memory for validation and security
Low-Power 1.7-V to 3.6-V Operation
Active, Low-power Active, Sleep, Low-power Sleep, Deep
Sleep, and Hibernate modes for fine-grained power
management
Deep Sleep mode current with 64 KB SRAM retention is 7 µA
with 3.3-V external supply and internal buck
On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter,
<1 µA quiescent current
Backup domain with 64 bytes of memory and Real-time Clock
(RTC)
Flexible Clocking Options
On-chip crystal oscillators (High-speed, 4 to 33 MHz, and
Watch crystal, 32 kHz)
Phase-locked Loop (PLL) for multiplying clock frequencies
8 MHz Internal Main Oscillator (IMO) with 2% accuracy
Ultra low-power 32-kHz Internal Low-speed Oscillator (ILO)
with 10% accuracy
Frequency Locked Loop (FLL) for multiplying IMO frequency
Serial Communication
Nine independent run-time
cation blocks (SCBs), each
reconfigurable serial communi-
is software configurable as I2C,
SPI, or UART
USB Full-Speed Dual-role Host and Device interface
Timing and Pulse-Width Modulation
Thirty-two Timer/Counter Pulse-Width Modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals
Up to 104 Programmable GPIOs
Drive modes, strengths, and slew rates are programmable
Six overvoltage tolerant (OVT) pins
Packages
124-BGA (Qualification in process)
80-WLCSP (in 0.33 and 0.43 mm heights). Thin 80-WLCSP
package (0.33 mm height) qualification is in process.
Audio Subsystem
I2S Interface; up to 192 ksps Word Clock
Two PDM channels for stereo digital microphones
QSPI Interface
Execute-In-Place (XIP) from external Quad SPI Flash
On-the-fly encryption and decryption
4 KB QSPI cache for greater XIP performance with lower power
Supports 1, 2, 4, and Dual-Quad interfaces
Errata: For information on silicon errata, see “Revision History” on page 63. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-21414 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 8, 2018




 PSoC61
PSoC® 6 MCU: PSoC 61
Datasheet
Programmable Analog
12-bit 1 Msps SAR ADC with differential and single-ended
modes and 16-Channel Sequencer with signal averaging
One 12-bit voltage mode DAC with < 5-µs settling time
Two opamps with low-power operation modes
Two low-power comparators that operate in Deep Sleep and
Hibernate modes.
Built-in temp sensor connected to ADC
Programmable Digital
12 programmable logic blocks, each with eight Macrocells and
an 8-bit data path (called universal digital blocks or UDBs)
Usable as drag-and-drop Boolean primitives (gates, registers),
or as Verilog programmable blocks
Cypress-provided peripheral component library using UDBs
with common functions such as SDIO, Communication
Peripherals such as LIN, UART, SPI, I2C, S/PDIF, Waveform
Generator, Pseudo-Random Sequence (PRS) generation, and
many other functions.
Smart I/O (Programmable I/O) blocks enable Boolean
operations on signals coming from, and going to, GPIO pins
Two ports with Smart_IO blocks, capability are provided; these
are available during Deep Sleep
Capacitive Sensing
Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR, liquid tolerance, and proximity sensing
Mutual Capacitance sensing (Cypress CSX) with dynamic
usage of both Self and Mutual sensing
Wake on Touch with very low current
Cypress-supplied software component makes capacitive
sensing design fast and easy
Automatic hardware tuning (SmartSense™)
Energy Profiler
Block that provides history of time spent in different power
modes
Allows software energy profiling to observe and optimize
energy consumption
PSoC Creator Design Environment
Integrated Development Environment provides schematic
design entry and build (with analog and digital automatic
routing) and code development and debugging
Applications Programming Interface (API Component) for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
After schematic entry, development can be done with
Arm-based industry-standard development tools
Configure in PSoC Creator and export to Arm/Keil or IAR IDEs
for code development and debugging
Supports industry standard Arm Trace Emulation Trace Module
Security Built into Platform Architecture
Multi-faceted secure architecture based on ROM-based root of
trust
Secure Boot uninterruptible until system protection attributes
are established
Authentication during boot using hardware hashing
Step-wise authentication of execution images
Secure execution of code in execute-only mode for protected
routines
All Debug and Test ingress paths can be disabled
Cryptography Accelerators
Hardware acceleration for Symmetric and Asymmetric
cryptographic methods (AES, 3DES, RSA, and ECC) and Hash
functions (SHA-512, SHA-256)
True Random Number Generator (TRNG) function
Document Number: 002-21414 Rev. *F
Page 2 of 64




 PSoC61
PSoC® 6 MCU: PSoC 61
Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate
it into your design. The following is an abbreviated list of resources for PSoC 6 MCU:
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 6 MCU Page
Application Notes cover a broad range of topics, from basic
to advanced level, and include the following:
AN210781: Getting Started with PSoC 6 MCU BLE
AN218241: PSoC 6 MCU Hardware Design Considerations
AN213924: PSoC 6 MCU Bootloader Guide
AN215656: PSoC 6 MCU Dual-Core CPU System Design
AN219434: Importing PSoC Creator Code into an IDE
AN219528: PSoC 6 MCU Power Reduction Techniques
AN221111: PSoC 6 MCU: Creating a Secure System
Code Examples provides PSoC Creator example projects for
different product features and usage.
Technical Reference Manuals (TRMs) provide detailed
descriptions of PSoC 6 MCU architecture and registers.
Development Tools
CY8CKIT-062-Wi-Fi-/BT supports the PSoC 62 series MCU
with WiFi and Bluetooth connectivity.
CY8CKIT-062-BLE supports the PSoC 63 series MCU with
Bluetooth Low-Energy (BLE) connectivity.
Training Videos: Visit www.cypress.com/training for a wide
variety of video training resources on PSoC Creator
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables you to design hardware and firmware
systems concurrently, based on PSoC 6 MCU. As shown below, with PSoC Creator, you can:
1. Explore the library of 200+ Components in PSoC Creator
2. Drag and drop Component icons to complete your hardware
system design in the main design workspace
3. Configure Components using the Component Configuration
Tools and the Component datasheets
4. Co-design your application firmware and hardware in the
PSoC Creator IDE or build project for 3rd party IDE
5. Prototype your solution with the PSoC 6 Pioneer Kits.If a
design change is needed, PSoC Creator and Components
enable you to make changes on the fly without the need for
hardware revisions.
Figure 1. PSoC Creator Schematic Entry and Components
 
Document Number: 002-21414 Rev. *F
Page 3 of 64



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