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Analog-to-Digital Converter. AD9689 Datasheet

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Analog-to-Digital Converter. AD9689 Datasheet
















AD9689 Converter. Datasheet pdf. Equivalent













Part

AD9689

Description

Dual Analog-to-Digital Converter



Feature


Data Sheet 14-Bit, 2.0 GSPS/2.6 GSPS, J ESD204B, Dual Analog-to-Digital Convert er AD9689 FEATURES 0.975 V, 1.9 V, an d 2.5 V dc supply operation JESD204B ( Subclass 1) coded serial digital output s Support for lane rates up to 16 Gbps per lane Noise density −152 dBFS/Hz a t 2.56 GSPS at full-scale voltage = 1.7 V p-p −154 dBFS/Hz at 2.56 GSPS at f ull-scale voltage = 2..
Manufacture

Analog Devices

Datasheet
Download AD9689 Datasheet


Analog Devices AD9689

AD9689; 0 V p-p −154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p −155.3 dBFS/Hz at 2.0 GSPS at full-scale volt age = 2.0 V p-p 1.55 W total power per channel at 2.56 GSPS (default settings) SFDR at 2.56 GSPS encode 73 dBFS at 1. 8 GHz AIN at −2.0 dBFS 59 dBFS at 5.5 3 GHz AIN at −2.0 dBFS full-scale vol tage = 1.1 V p-p SNR at 2.56 GSPS encod e 9 GHz analog input full.


Analog Devices AD9689

power bandwidth (−3 dB) Amplitude det ect bits for efficient AGC implementati on Programmable FIR filters for analog channel loss equalization 2 integrated, wideband digital processors per channe l 48-bit NCO Programmable decimation ra tes Phase coh .


Analog Devices AD9689

.





Part

AD9689

Description

Dual Analog-to-Digital Converter



Feature


Data Sheet 14-Bit, 2.0 GSPS/2.6 GSPS, J ESD204B, Dual Analog-to-Digital Convert er AD9689 FEATURES 0.975 V, 1.9 V, an d 2.5 V dc supply operation JESD204B ( Subclass 1) coded serial digital output s Support for lane rates up to 16 Gbps per lane Noise density −152 dBFS/Hz a t 2.56 GSPS at full-scale voltage = 1.7 V p-p −154 dBFS/Hz at 2.56 GSPS at f ull-scale voltage = 2..
Manufacture

Analog Devices

Datasheet
Download AD9689 Datasheet




 AD9689
Data Sheet
14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9689
FEATURES
0.975 V, 1.9 V, and 2.5 V dc supply operation
JESD204B (Subclass 1) coded serial digital outputs
Support for lane rates up to 16 Gbps per lane
Noise density
−152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p
−154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p
−154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p
−155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p
1.55 W total power per channel at 2.56 GSPS (default settings)
SFDR at 2.56 GSPS encode
73 dBFS at 1.8 GHz AIN at −2.0 dBFS
59 dBFS at 5.53 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
SNR at 2.56 GSPS encode
9 GHz analog input full power bandwidth (−3 dB)
Amplitude detect bits for efficient AGC implementation
Programmable FIR filters for analog channel loss equalization
2 integrated, wideband digital processors per channel
48-bit NCO
Programmable decimation rates
Phase coherent NCO switching
Up to 4 channels available
Serial port control
Supports 100 MHz SPI writes and 50 MHz SPI reads
Integer clock with divide by 2 and divide by 4 options
Flexible JESD204B lane configurations
On-chip dither
59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS
53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
SFDR at 2.0 GSPS encode
78 dBFS at 900 MHz AIN at −2.0 dBFS
62 dBFS at 5.53 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
SNR at 2.0 GSPS encode
APPLICATIONS
Diversity multiband and multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A
Electronic test and measurement systems
Phased array radar and electronic warfare
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
62.7 dBFS at 900 MHz AIN at −2.0 dBFS
53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR
(0.975V) (1.9V) (2.5V) (0.975V)
DVDD DRVDD1 DRVDD2 SPIVDD
(0.975V) (0.975V) (1.9V)
(1.9V)
VIN+A
VIN–A
VIN+B
VIN–B
VREF
PDWN/STBY
SYSREF±
CLK+
CLK–
BUFFER
ADC
CORE
14
FAST
DETECT
SIGNAL
MONITOR
BUFFER
ADC
CORE
14
JESD204B
SUBCLASS 1
CONTROL
CLOCK
DISTRIBUTION
÷2
÷4
DIGITAL DOWN-
CONVERTER
DIGITAL DOWN-
CONVERTER
SPI AND
CONTROL
REGISTERS
JESD204B
LINK
AND
Tx
OUTPUTS
8
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SERDOUT4±
SERDOUT5±
SERDOUT6±
SERDOUT7±
GPIO MUX
AD9689
SYNCINB±
FD_A/GPIO_A0
GPIO_A1
FD_B/GPIO_B0
GPIO_B1
AGND
SDIO SCLK CSB
Figure 1.
DRGND DGND
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




 AD9689
AD9689
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Product Highlights ........................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
AC Specifications.......................................................................... 6
Digital Specifications ................................................................... 8
Switching Specifications .............................................................. 9
Timing Specifications ................................................................ 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 16
2.0 GSPS....................................................................................... 16
2.6 GSPS....................................................................................... 21
Equivalent Circuits ......................................................................... 26
Theory of Operation ...................................................................... 28
ADC Architecture ...................................................................... 28
Analog Input Considerations.................................................... 28
Voltage Reference ....................................................................... 31
DC Offset Calibration................................................................ 32
Clock Input Considerations ...................................................... 32
Power-Down and Standby Mode ............................................. 35
Temperature Diode .................................................................... 35
ADC Overrange and Fast Detect.................................................. 37
ADC Overrange.......................................................................... 37
Fast Threshold Detection (FD_A and FD_B) ........................ 37
ADC Application Modes and JESD204B Tx Converter Mapping
........................................................................................................... 38
Programmable FIR Filters ............................................................. 40
Supported Modes........................................................................ 40
Programming Instructions........................................................ 42
Digital Downconverter (DDC)..................................................... 44
DDC I/Q Input Selection .......................................................... 44
DDC I/Q Output Selection ....................................................... 44
DDC General Description ........................................................ 44
DDC Frequency Translation..................................................... 47
DDC Decimation Filters ........................................................... 55
DDC Gain Stage ......................................................................... 61
DDC Complex to Real Conversion ......................................... 61
DDC Mixed Decimation Settings ............................................ 62
DDC Example Configurations ................................................. 64
DDC Power Consumption........................................................ 67
Signal Monitor ................................................................................ 68
SPORT over JESD204B.............................................................. 69
Digital Outputs ............................................................................... 71
Introduction to the JESD204B Interface ................................. 71
JESD204B Overview .................................................................. 71
Functional Overview ................................................................. 72
JESD204B Link Establishment ................................................. 72
Physical Layer (Driver) Outputs .............................................. 74
fS × 4 Mode .................................................................................. 75
Setting Up the AD9689 Digital Interface................................. 76
Deterministic Latency.................................................................... 83
Subclass 0 Operation.................................................................. 83
Subclass 1 Operation.................................................................. 83
Multichip Synchronization............................................................ 85
Normal Mode.............................................................................. 85
Timestamp Mode ....................................................................... 85
SYSREF Input.............................................................................. 87
SYSREF± Setup/Hold Window Monitor................................. 89
Latency............................................................................................. 91
End to End Total Latency.......................................................... 91
Example Latency Calculations.................................................. 91
LMFC Referenced Latency........................................................ 91
Test Modes....................................................................................... 93
ADC Test Modes ........................................................................ 93
JESD204B Block Test Modes .................................................... 94
Serial Port Interface........................................................................ 96
Configuration Using the SPI..................................................... 96
Hardware Interface..................................................................... 96
SPI Accessible Features.............................................................. 96
Memory Map .................................................................................. 97
Reading the Memory Map Register Table............................... 97
Memory Map Register Details.................................................. 98
Applications Information ............................................................ 132
Rev. A | Page 2 of 134




 AD9689
Data Sheet
Power Supply Recommendations .......................................... 132
Layout Guidelines .................................................................... 133
AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8)........... 133
REVISION HISTORY
10/2017—Rev. 0 to Rev. A
Added 2.0 GSPS............................................................. Throughout
Changes to Features Section ............................................................1
Changes to Product Highlights Section .........................................4
Changes to Table 1 ............................................................................5
Changes to Table 2 ............................................................................6
Changes to Table 4 ............................................................................9
Added 2.0 GSPS Section and Figure 6 to Figure 11; Renumbered
Sequentially ......................................................................................16
Added Figure 12 to Figure 17 ........................................................17
Added Figure 18 to Figure 23 ........................................................18
Added Figure 24 through Figure 29..............................................19
Added Figure 30 through Figure 35..............................................20
Added 2.6 GSPS Section.................................................................21
Change to Figure 41 ........................................................................21
Change to Figure 45 ........................................................................22
Changes to Figure 52 and Figure 53 .............................................23
Changes to Figure 54, Figure 55, Figure 56, Figure 58, and
Figure 59 ...........................................................................................24
Changes to Figure 60 and Figure 61 .............................................25
AD9689
Outline Dimensions......................................................................134
Ordering Guide .........................................................................134
Changes to Figure 67 Caption .......................................................26
Changes to Table 10 ........................................................................30
Changes to Figure 87 ......................................................................32
Changes to Figure 96 Caption .......................................................35
Changes to Programming Instructions Section..........................42
Added Table 28; Renumbered Sequentially.................................67
Changes to Table 29 Title ...............................................................67
Changes to De-Emphasis Section .................................................74
Changes to Figure 142 ....................................................................82
Changes to Reading the Memory Map Register Table Section.......97
Changes to Address 0x0006, Table 46 ..........................................98
Changes to Address 0x010A, Table 47 .........................................99
Changes to Table 50 ......................................................................105
Changes to Table 51 ......................................................................117
Changes to Power Supply Recommendations Section, Figure 157,
and Figure 158 ...............................................................................132
Changes to Ordering Guide.........................................................134
9/2017—Revision 0: Initial Version
Rev. A | Page 3 of 134




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