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PWM Regulator. ISL6277A Datasheet

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PWM Regulator. ISL6277A Datasheet






ISL6277A Regulator. Datasheet pdf. Equivalent






ISL6277A Regulator. Datasheet pdf. Equivalent


ISL6277A

Part

ISL6277A

Description

Multiphase PWM Regulator



Feature


DATASHEET ISL6277A Multiphase PWM Regul ator for AMD Fusion™ Mobile CPUs Usin g SVI 2.0 FN8322 Rev 2.00 December 4, 2015 The ISL6277A is fully compliant w ith AMD Fusion SVI 2.0 and provides a c omplete solution for microprocessor and graphics processor core power. The ISL 6277A controller supports two Voltage R egulators (VRs) with three integrated g ate drivers and two .
Manufacture

Renesas

Datasheet
Download ISL6277A Datasheet


Renesas ISL6277A

ISL6277A; optional external drivers for maximum fl exibility. The Core VR can be configure d for 3-, 2-, or 1-phase operation whil e the Northbridge VR supports 2- or 1-p hase configurations. The two VRs share a serial control bus to communicate wit h the AMD CPU and achieve lower cost an d smaller board area compared with two- chip solutions. The PWM modulator is ba sed on Intersil’s .


Renesas ISL6277A

Robust Ripple Regulator R3™ Technology . Compared to traditional modulators, t he R3™ modulator can automatically ch ange switching frequency for faster tra nsient settling time during load transi ents and improved light load efficiency . The ISL6277A has se .

Part

ISL6277A

Description

Multiphase PWM Regulator



Feature


DATASHEET ISL6277A Multiphase PWM Regul ator for AMD Fusion™ Mobile CPUs Usin g SVI 2.0 FN8322 Rev 2.00 December 4, 2015 The ISL6277A is fully compliant w ith AMD Fusion SVI 2.0 and provides a c omplete solution for microprocessor and graphics processor core power. The ISL 6277A controller supports two Voltage R egulators (VRs) with three integrated g ate drivers and two .
Manufacture

Renesas

Datasheet
Download ISL6277A Datasheet




 ISL6277A
DATASHEET
ISL6277A
Multiphase PWM Regulator for AMD Fusion™ Mobile CPUs Using SVI 2.0
FN8322
Rev 2.00
December 4, 2015
The ISL6277A is fully compliant with AMD Fusion SVI 2.0 and
provides a complete solution for microprocessor and graphics
processor core power. The ISL6277A controller supports two
Voltage Regulators (VRs) with three integrated gate drivers and
two optional external drivers for maximum flexibility. The Core
VR can be configured for 3-, 2-, or 1-phase operation while the
Northbridge VR supports 2- or 1-phase configurations. The two
VRs share a serial control bus to communicate with the AMD
CPU and achieve lower cost and smaller board area compared
with two-chip solutions.
The PWM modulator is based on Intersil’s Robust Ripple
Regulator R3™ Technology. Compared to traditional
modulators, the R3™ modulator can automatically change
switching frequency for faster transient settling time during
load transients and improved light load efficiency.
The ISL6277A has several other key features. Both outputs
support DCR current sensing with single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. Both outputs utilize remote voltage sense, adjustable
switching frequency, OC protection and power-good.
Applications
• AMD fusion CPU/GPU core power
• Notebook computers
Features
• Supports AMD SVI 2.0 serial data bus interface
- Serial VID clock frequency range 100kHz to 25MHz
• Dual output controller with integrated drivers
- Two dedicated core drivers
- One programmable driver for either Core or Northbridge
• Precision voltage regulation
- 0.5% system accuracy over-temperature
- 0.5V to 1.55V in 6.25mV steps
- Enhanced load line accuracy
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Programmable 1-, 2- or 3-phase for the core output and 1- or
2-phase for the Northbridge output
• Adaptive body diode conduction time reduction
• Superior noise immunity and transient response
• Output current and voltage telemetry
• Differential remote voltage sensing
• High efficiency across entire load range
• Programmable slew rate
• Programmable VID offset and droop on both outputs
• Programmable switching frequency for both outputs
• Excellent dynamic current balance between phases
• Protection: OCP/WOC, OVP, PGOOD and thermal monitor
• Small footprint 48 Ld 6x6 QFN package
- Pb-free (RoHS compliant)
Core Performance
100
90
80
70
60
50
40
30
20
10
0
0
VIN = 8V
VIN = 12V
VIN = 19V
VOUT CORE = 1.1V
5 10 15 20 25 30 35 40 45 50 55
IOUT (A)
FIGURE 1. EFFICIENCY vs LOAD
1.12
1.10
1.08
1.06
1.04
1.02
VIN = 12V
VIN = 8V
1.00
VIN = 19V
0.98
VOUT CORE = 1.1V
0.96 0 5 10 15 20 25 30 35 40 45 50 55
IOUT (A)
FIGURE 2. VOUT vs LOAD
FN8322 Rev 2.00
December 4, 2015
Page 1 of 38




 ISL6277A
ISL6277A
Table of Contents
Simplified Application Circuit for High Power
CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Simplified Application Circuit with 3 Internal Drivers
Used for Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Simplified Application Circuit for Mid-Power CPUs
[2+1 Configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Simplified Application Circuit for Low Power CPUs
[1+1 Configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .11
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Recommended Operating Conditions . . . . . . . . . . . . . . . . .11
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .13
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . 15
Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage Regulation and Load Line Implementation . . . . . . . 16
Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FB2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Adaptive Body Diode Conduction Time Reduction . . . . . . . . 20
Resistor Configuration Options. . . . . . . . . . . . . . . . . . . . . . .20
VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Floating DriverX and PWM_Y Configuration . . . . . . . . . . . . . 21
VID-on-the-Fly Slew Rate Selection. . . . . . . . . . . . . . . . . . . . . 21
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . 22
Pre-PWROK Metal VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . . 23
SVI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . . 25
Dynamic Offset Trim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Telemetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Thermal Monitor [NTC, NTC_NB]. . . . . . . . . . . . . . . . . . . . . . . 27
Fault Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . 28
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . 30
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Thermal Monitor Component Selection . . . . . . . . . . . . . . . . . 32
Bootstrap Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . 33
Optional FCCM_NB Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FN8322 Rev 2.00
December 4, 2015
Page 2 of 38



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