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ADSP-BF561SBB500 Dataheets PDF



Part Number ADSP-BF561SBB500
Manufacturers Analog Devices
Logo Analog Devices
Description Blackfin Embedded Symmetric Multi-Processor
Datasheet ADSP-BF561SBB500 DatasheetADSP-BF561SBB500 Datasheet (PDF)

a FEATURES Preliminary Technical Data Dual Symmetric 600 Mhz High Performance Blackfin Core 328 KBytes of On-chip Memory (See Memory Info on Page 3) Each Blackfin Core Includes: Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs, 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of Programming and Compiler-Friendly Support Advanced Debug, Trace, and Performance- Monitoring 0.8 - 1.2V core VDD with On-Chip Voltage Regulation 3.3V and 2.5V Tolerant I/O 256-Ball Mini BGA and 29.

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a FEATURES Preliminary Technical Data Dual Symmetric 600 Mhz High Performance Blackfin Core 328 KBytes of On-chip Memory (See Memory Info on Page 3) Each Blackfin Core Includes: Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs, 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of Programming and Compiler-Friendly Support Advanced Debug, Trace, and Performance- Monitoring 0.8 - 1.2V core VDD with On-Chip Voltage Regulation 3.3V and 2.5V Tolerant I/O 256-Ball Mini BGA and 297-Ball PBGA Package Options Blackfin® Embedded Symmetric Multi-Processor ADSP-BF561 PERIPHERALS Two Parallel Input/Output Peripheral Interface Units Supporting ITU-R 656 Video and Glueless Interface to ADI Analog Front End ADCs Two Dual Channel, Full Duplex Synchronous Serial Ports Supporting Eight Stereo I2S Channels Dual 16 Channel DMA Controllers and one internal memory DMA controller 12 General Purpose 32-bit Timer/Counters, with PWM Capability SPI-Compatible Port UART with Support for IrDA® Dual Watchdog Timers 48 Programable Flags On-Chip Phase Locked Loop Capable of 1x to 63x Frequency Multiplication IRQ CTRL/ TIMER VOLTAGE REGULATOR B L1 INSTRUCTION MEMORY MMU L1 DATA MEMORY B L1 INSTRUCTION MEMORY MMU L1 DATA MEMORY IRQ CTRL/ TIMER JTAG TEST EMULATION UART IRDA® SPI L2 SRAM 128 KBYTES SPORT0 CORE SYSTEM / BUS INTERFACE IMDMA CONTROLLER SPORT1 EAB DMA CONTROLLER1 32 DMA CONTROLLER2 BOOT ROM 32 DAB DAB PAB 16 16 GPIO TIMERS EXTERNAL PORT FLASH/SDRAM CONTROL PPI PPI Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. ADSP-BF561 TABLE OF CONTENTS General Description ................................................. 3 Portable Low-Power Architecture ............................. 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 4 Internal (On-chip) Memory ................................. 4 External (Off-Chip) Memory ................................ 5 I/O Memory Space ............................................. 6 Booting ........................................................... 6 Event Handling ................................................. 6 Core Event Controller (CEC) ................................ 6 System Interrupt Controller (SIC) .......................... 6 Event Control ................................................... 7 DMA Controllers .................................................. 8 WatchDog Timers ................................................ 8 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Ports ........................ 9 UART Port .......................................................... 9 Programmable Flags (PFx) .................................... 10 Timers ............................................................. 10 Parallel Peripheral Interface ................................... 10 General Purpose Mode Descriptions .................... 10 Input Mode .................................................... 10 ITU -R 656 Mode Descriptions ........................... 10 Active Video Only Mode ................................... 10 Vertical Blanking Interval Mode .......................... 11 Entire Field Mode ............................................ 11 Dynamic Power Management ................................ 11 Full-On Operating Mode – Maximum Performance . 11 Active Operating Mode – Moderate Power Savings .. 11 Hibernate Operating Mode—Maximum Static Power Savings ....................................................... 11 Sleep Operating Mode – High Power Savings ......... 11 Deep Sleep Operating Mode – Max. Power Savings .. 11 Power Savings ................................................. 12 Voltage Regulation .............................................. 12 Clock Signals ..................................................... 13 Booting Modes ................................................... 13 Instruction Set Description ................................... 14 Preliminary Technical Data Development Tools .............................................. 14 Designing an Emulator-Compatible Processor Board (Target) ................................... 15 Additional Information .................................


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