ADSP2183

a FEATURES PERFORMANCE 19 ns Instruction Cycle Time from 26.32 MHz Crystal @ 3.3 Volts 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 300 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 80K Bytes of On-Chip RAM, Configured as 16K Words On-Chip Program Memory RAM 16K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 128-Lead LQFP, 144-Ball Mini-BGA SYSTEM INTERFACE 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory 4 MByte Memory Interface for Storage of Data Tables and Program Overlays 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers I/O Memory Interface with 2048 Locations Supports Parallel Peripherals Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic ...