AD9208

Data Sheet 14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter AD9208 FEATURES JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane 1.65 W total power per channel at 3 GSPS (default settings) Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO 4 cascaded half-band filters Phase coherent NCO switching Up to 4 channels available Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither APPLICATIONS Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers PROGRAMMABLE FIR FILTER CROSSBAR MUX CROSSBAR MUX 15547-001 AVDD1 (0.975V) AVDD2 (1.9V) FUNCTIONAL BLOCK DIAGRAM AVDD3 AVDD1_SR (2.5V) (0.975V) DVDD DRVDD1 DRVDD2 (0.975V) (0.975V) (1.9V) SPIVDD (1.9V) VIN+A VIN–A VIN+B VIN–B VREF PDWN/STBY SYSREF± CLK+ CLK– BUFFER ADC CORE 14 FAST DETECT SIGNAL MONITOR BUFFER ADC CORE 14 JESD204B ...