IS42S81600F Datasheet (data sheet) PDF





IS42S81600F Datasheet, 128Mb SYNCHRONOUS DRAM

IS42S81600F   IS42S81600F  

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IS42/45S81600F IS42/45S16800F 16Mx8, 8Mx 16 128Mb SYNCHRONOUS DRAM JULY 2015 F EATURES • Clock frequency: 200, 166 , 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply Vdd Vddq IS42/45S81600F 3.3V 3.3V IS42/45S16800F 3.3V 3.3V • LVTTL interface • Programmab le burst length – (1, 2, 4, 8, full p age) • Programmable burst sequence: Sequential/Interleave • Auto Refre sh (CBR) • Self Refresh • 4096 refresh cycles every 16 ms (A2 grade) o r 64 ms (Commercial, Industrial, A1 gra de) • Random column address every clock cycle

IS42S81600F Datasheet, 128Mb SYNCHRONOUS DRAM

IS42S81600F   IS42S81600F  
• Programmable CAS latency (2, 3 cl ocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Temperature Ranges: Commercial (0oC to +70oC) Indu strial (-40oC to +85oC) Automotive, A1 (-40oC to +85oC) Automotive, A2 (-40oC to +105oC) OVERVIEW ISSI's 128Mb Synch ronous DRAM achieves high-speed data t ransfer using pipeline architecture. Al l inputs and outputs signals refer to t he rising edge of the clock input. The 128Mb SDRAM is organized as follows. I S42/45S81600F IS42/45S16800F 4M x8 x4 Banks 2M x16 x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA KEY TIMING PARAMETERS Parameter -5 - 6 -7 Unit Clk Cycle Time CAS Latenc y = 3 CAS Latency = 2 5 6 7 ns 10 10 7.5 ns Clk Fr equency CAS Latency = 3 CAS Latency = 2 200 166 143 Mhz 1 00 100 133 Mhz Access Time from Clock CAS Latency = 3 5 5.4 5.4 ns CAS Latency = 2 6. 5 6.5 5.4 ns Copyright © 2015 In tegrated Silicon Solution, Inc. All rig hts reserved. ISSI reserves the right t o make changes to this specification an d its products at any time without noti ce. ISSI assumes no liability arising o ut of the application or use of any information, products or








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