ZL40230

Data Sheet ZL40230 Low Skew, Low Additive Jitter 10 output LVPECL/LVDS/HCSL Fanout Buffer with one LVCMOS output Features 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal Ten differential LVPECL/LVDS/HCSL outputs One LVCMOS output Ultra-low additive jitter: 24fs (integration band: 12kHz to 20MHz at 625MHz clock frequency) Supports clock frequencies from 0 to 1.6GHz Supports 2.5V or 3.3V power supplies on LVPECL/LVDS/HCSL outputs Supports 1.5V, 1.8V, 2.5V or 3.3V on LVCMOS output Embedded Low Drop Out (LDO) Voltage regulator provides superior Power Supply Noise Rejection Maximum output to output skew of 40ps Device controlled via SPI or hardware control pins Ordering Information ZL40230LDG1 ZL40230LDF1 48 Pin QFN Trays 48 pin QFN Tape and Reel Applications Package size: 7 x 7 mm -40C to +85C -40C to +85C General purpose clock distribution Low jitter clock trees Logic translation Clock and data signal restoration Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC PCI Express generation 1/2/3/4 clock distribution Wireless communications High performance microprocessor clock distribution Test Equipment SEL LVCMOS_OE/ SPI_CS_b IN_SEL0/ SPI_CLK IN_SEL1/ SPI_SDI OUTB_TYPE_SEL0/ SPI_SDO OUTB_TYPE_SEL1 OUTA_TYPE_SEL0 OUTA_TYPE_SEL1 IN0_p IN0_n IN1_p IN1_n XOUT XIN OE SPI_CS_b IN_SEL0...