ZL40231

Data Sheet ZL40231 Low Skew, Low Additive Jitter, 10 output LVPECL/LVDS/HCSL Fanout Buffer with one LVCMOS output Features 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal Ten differential LVPECL/LVDS/HCSL outputs One LVCMOS output Ultra-low additive jitter: 24fs (integration band: 12kHz to 20MHz at 625MHz clock frequency) Supports clock frequencies from 0 to 1.6GHz Supports 2.5V or 3.3V power supplies on LVPECL, LVDS or HCSL outputs Supports 1.5V, 1.8V, 2.5V or 3.3V on LVCMOS outputs Embedded Low Drop Out (LDO) Voltage regulator provides superior Power Supply Noise Rejection Maximum output to output skew of 40ps Device controlled via control pins Ordering Information ZL40231LDG1 ZL40231LDF1 48 Pin QFN Trays 48 pin QFN Tape and Reel Applications Package size: 7 x 7 mm -40C to +85C -40C to +85C General purpose clock distribution Low jitter clock trees Logic translation Clock and data signal restoration Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC PCI Express generation 1/2/3/4 clock distribution Wireless communications High performance microprocessor clock distribution Test Equipment OUTA_TYPE_SEL0 OUTA_TYPE_SEL1 IN_SEL0 IN_SEL1 IN0_p IN0_n IN1_p IN1_n XOUT XIN OUTB_TYPE_SEL0 OUTB_TYPE_SEL1 LVCMOS_OE OUT_A_TYPE_SEL[1:0] BANK A OUTPUT 00 LVECL 01 LVDS 10 HCSL 11 HIGH-Z Z...