ZL40260 Datasheet (data sheet) PDF





ZL40260 Datasheet, Low Additive Jitter 2 x10 LVPECL Fanout Buffer

ZL40260   ZL40260  

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Data Sheet ZL40260 Low Skew, Low Addit ive Jitter 2 x10 LVPECL Fanout Buffer Features  Two inputs accept any diff erential (LVPECL, HCSL, LVDS, SSTL, CML ) or single ended LVCMOS signal  Ten 2.5V/3.3V LVPECL outputs  Ultra-low additive jitter: 53fs for 125 MHz cloc k measured in 12KHz to 20MHz band  S upports clock frequencies from 0 to 1.6 GHz  Supports 2.5V or 3.3V power su

ZL40260 Datasheet, Low Additive Jitter 2 x10 LVPECL Fanout Buffer

ZL40260   ZL40260  
pplies  Embedded Low Drop Out (LDO) V oltage regulator provides superior Powe r Supply Noise Rejection  Maximum ou tput to output skew of 50ps  Maximum input to output delay of 1.2ns  Sma ll input to output delay variation over voltage, temperature and process of 0. 34ns  Fast rise and fall times of 16 8ps  Phase noise floor below -160dB/ Hz for 125MHz clock Ordering Informatio








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