ZL40260

Data Sheet ZL40260 Low Skew, Low Additive Jitter 2 x10 LVPECL Fanout Buffer Features  Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML) or single ended LVCMOS signal  Ten 2.5V/3.3V LVPECL outputs  Ultra-low additive jitter: 53fs for 125 MHz clock measured in 12KHz to 20MHz band  Supports clock frequencies from 0 to 1.6GHz  Supports 2.5V or 3.3V power supplies  Embedded Low Drop Out (LDO) Voltage regulator provides superior Power Supply Noise Rejection  Maximum output to output skew of 50ps  Maximum input to output delay of 1.2ns  Small input to output delay variation over voltage, temperature and process of 0.34ns  Fast rise and fall times of 168ps  Phase noise floor below -160dB/Hz for 125MHz clock Ordering Information ZL40260LDG1 ZL40260LDF1 ZL40260QGG1 ZL40260QGF1 32 Pin QFN Trays 32 pin QFN Tape and Reel 32 pin eTQFP Trays 32 pin eTQFP Tape and Reel Package size: 5 x 5 mm QFN and 7 x 7 mm eTQFP -40C to +85C -40C to +85C Applications  General purpose clock distribution  Low jitter clock trees  Logic translation  Clock and data signal restoration  Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC  PCI Express generation 1/2/3/4 clock distribution  Wireless communications  High performance microprocessor clock distribution  Test equipment CLK_SEL IN0_p IN0_n IN1_p IN1_n Vbb ZL40260 September 2017 © 2017 Microsemi Corporation Figure 1. Functional Block Diagram ZL40260 OUT0_p OUT0_n OUT1_p OUT1_n OUT2_p OUT2_n...