ZL40240 Datasheet (data sheet) PDF





ZL40240 Datasheet, Ten LVCMOS Output Low Additive Jitter Fanout Buffer

ZL40240   ZL40240  

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Data Sheet ZL40240 Ten LVCMOS Output L ow Additive Jitter Fanout Buffer Featu res  3 to 1 input Multiplexer: Two i nputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a sin gle ended signal and the third input ac cepts a crystal or a single ended signa l  Ten 1.5V/1.8V/2.5V/3.3V LVCMOS ou tputs  Supports frequencies from 0 t o 250MHz  Ultra-low system level add itive jitter: 17fs (12kHz to 20MHz)  Ultra-low noise floor of -170dBc/Hz Supports crystals from 8MHz to 160MHz  Supports 2.5V or 3.3V power suppli es  Output to output skew of 30ps (t ypical)  Input to output delay of 2n s (typical)  SPI or Hardware control Orde

ZL40240 Datasheet, Ten LVCMOS Output Low Additive Jitter Fanout Buffer

ZL40240   ZL40240  
ring Information ZL40240LDG1 ZL40240LDF 1 32 Pin QFN Trays 32 pin QFN Tape and Reel Package size: 5 x 5 mm -40C t o +85C Applications  General pur pose clock distribution  Low jitter clock trees  Logic translation  C lock and data signal restoration  Wi red and Wireless communications  Hig h performance microprocessor clock dist ribution  Medical Imaging  Test e quipment SEL OE/SPI_CS_b IN_SEL0/ SPI_ CLK IN_SEL1/ SPI_SDIO IN0_p IN0_n IN1_p IN1_n XOUT XIN OE SPI_CS_b IN_SEL0 SP I_CLK IN_SEL1 SPI_SDIO SPI Slave xtal_ buf_gain[7:0] xtal_drive_level[7:0] xta l_load_cap[7:0] input_select[1:0] outpu t_drive_low output_enable[4:0] output_e nable[9:5] driver_strength[4:0] driver_ strength[9:5] Device ID 00 01 SYNC 10 11 ZL40240 February 2017 © 2017 Micr osemi Corporation Figure 1. Functional Block Diagram ZL40240 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 1 Table of Contents Data Sheet ZL40240 Features.............................. ....................................... ....................................... ......................... 1 Table of Co ntents ................................ ....................................... ....................................... ........ 2 Pin Diagram ................ ........................................................................








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