ZL40240

Data Sheet ZL40240 Ten LVCMOS Output Low Additive Jitter Fanout Buffer Features  3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal  Ten 1.5V/1.8V/2.5V/3.3V LVCMOS outputs  Supports frequencies from 0 to 250MHz  Ultra-low system level additive jitter: 17fs (12kHz to 20MHz)  Ultra-low noise floor of -170dBc/Hz  Supports crystals from 8MHz to 160MHz  Supports 2.5V or 3.3V power supplies  Output to output skew of 30ps (typical)  Input to output delay of 2ns (typical)  SPI or Hardware control Ordering Information ZL40240LDG1 ZL40240LDF1 32 Pin QFN Trays 32 pin QFN Tape and Reel Package size: 5 x 5 mm -40C to +85C Applications  General purpose clock distribution  Low jitter clock trees  Logic translation  Clock and data signal restoration  Wired and Wireless communications  High performance microprocessor clock distribution  Medical Imaging  Test equipment SEL OE/SPI_CS_b IN_SEL0/ SPI_CLK IN_SEL1/ SPI_SDIO IN0_p IN0_n IN1_p IN1_n XOUT XIN OE SPI_CS_b IN_SEL0 SPI_CLK IN_SEL1 SPI_SDIO SPI Slave xtal_buf_gain[7:0] xtal_drive_level[7:0] xtal_load_cap[7:0] input_select[1:0] output_drive_low output_enable[4:0] output_enable[9:5] driver_strength[4:0] driver_strength[9:5] Device ID 00 01 SYNC 10 11 ZL40240 February 2017 © 2017 Microsemi Corporation Figure 1. Functional Block Diagram ZL40240 OUT0 OUT1 OUT2 OUT3 OUT4 OU...