NPIC6C596 Datasheet (data sheet) PDF





NPIC6C596 Datasheet, Power logic 8-bit shift register

NPIC6C596   NPIC6C596  

Search Keywords: NPIC6C596, datasheet, pdf, nexperia, Power, logic, 8-bit, shift, register, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

NPIC6C596 Power logic 8-bit shift regis ter; open-drain outputs Rev. 2 — 4 J uly 2013 Product data sheet 1. Genera l description The NPIC6C596 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and o pen-drain outputs. Both the shift and s torage register have separate clocks. T he device features a serial input (DS) and a serial output (Q7S) to enable cas cading and an asynchronous reset MR inp ut. A LOW on MR resets both the shift r egister and storage register. Data is s hifted on the LOW-to-HIGH transitions o f the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH

NPIC6C596 Datasheet, Power logic 8-bit shift register

NPIC6C596   NPIC6C596  
transition of the STCP input. If both cl ocks are connected together, the shift register is always one clock pulse ahea d of the storage register. To provide a dditional hold time in cascaded applica tions, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the storage register drives the gate of the output extended-drain NMOS (EDN MOS) transistor whenever the output ena ble input (OE) is LOW. A HIGH on OE cau ses the outputs to assume a high-impeda nce OFF-state. Operation of the OE inpu t does not affect the state of the regi sters. The open-drain outputs are 33 V/ 100 mA continuous current extended-drai n NMOS transistors designed for use in systems that require moderate load powe r such as LEDs. Integrated voltage clam ps in the outputs provide protection ag ainst inductive transients making the d evice suitable for power driver applica tions such as relays, solenoids and oth er low-current or medium-voltage loads. 2. Features and benefits  Specified from 40 C to +125 C  Low R DSon  Eight Power EDNMOS transistor outputs of 100 mA continuous current 250 mA current limit capability  O utput clamping voltage 33 V  30 mJ a valanche energy capability  Enhanced cascading for multiple stages  All registers cleared with single input  Low power consumption  ESD protect








@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)