NPIC6C596A Datasheet (data sheet) PDF





NPIC6C596A Datasheet, Power logic 8-bit shift register

NPIC6C596A   NPIC6C596A  

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NPIC6C596A Power logic 8-bit shift regi ster; open-drain outputs Rev. 1 — 23 October 2013 Product data sheet 1. G eneral description The NPIC6C596A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clo cks. The device features a serial input (DS) and a serial output (Q7S

NPIC6C596A Datasheet, Power logic 8-bit shift register

NPIC6C596A   NPIC6C596A  
) to enable cascading and an asynchronou s reset MR input. A LOW on MR resets bo th the shift register and storage regis ter. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The dat a in the shift register is transferred to the storage register on a LOW-to-HIG H transition of the STCP input. If both clocks are connected together, the shi ft register is always one cl








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