NPIC6C596A-Q100 Datasheet (data sheet) PDF





NPIC6C596A-Q100 Datasheet, Power logic 8-bit shift register

NPIC6C596A-Q100   NPIC6C596A-Q100  

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NPIC6C596A-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 1 18 October 2013 Product data sheet 1. General description The NPIC6C596A- Q100 is an 8-bit serial-in/serial or pa rallel-out shift register with a storag e register and open-drain outputs. Both the shift and storage register have se parate clocks. The device features a se rial input (DS) and a serial o

NPIC6C596A-Q100 Datasheet, Power logic 8-bit shift register

NPIC6C596A-Q100   NPIC6C596A-Q100  
utput (Q7S) to enable cascading and an a synchronous reset MR input. A LOW on MR resets both the shift register and sto rage register. Data is shifted on the L OW-to-HIGH transitions of the SHCP inpu t. The data in the shift register is tr ansferred to the storage register on a LOW-to-HIGH transition of the STCP inpu t. If both clocks are connected togethe r, the shift register is alw








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