NPIC6C596-Q100 Datasheet (PDF)





NPIC6C596-Q100 Datasheet - Power logic 8-bit shift register

NPIC6C596-Q100   NPIC6C596-Q100  

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NPIC6C596-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 2 4 July 2013 Product data sheet 1. G eneral description The NPIC6C596-Q100 i s an 8-bit serial-in/serial or parallel -out shift register with a storage regi ster and open-drain outputs. Both the s hift and storage register have separate clocks. The device features a serial i nput (DS) and a serial output

NPIC6C596-Q100 Datasheet - Power logic 8-bit shift register

NPIC6C596-Q100   NPIC6C596-Q100  
(Q7S) to enable cascading and an asynchr onous reset MR input. A LOW on MR reset s both the shift register and storage r egister. Data is shifted on the LOW-to- HIGH transitions of the SHCP input. The data in the shift register is transfer red to the storage register on a LOW-to -HIGH transition of the STCP input. If both clocks are connected together, the shift register is always on








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