DatasheetsPDF.com

NPIC6C596-Q100 Dataheets PDF



Part Number NPIC6C596-Q100
Manufacturers nexperia
Logo nexperia
Description Power logic 8-bit shift register
Datasheet NPIC6C596-Q100 DatasheetNPIC6C596-Q100 Datasheet (PDF)

NPIC6C596-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 3 — 22 June 2020 Product data sheet 1. General description The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage re.

  NPIC6C596-Q100   NPIC6C596-Q100


Document
NPIC6C596-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 3 — 22 June 2020 Product data sheet 1. General description The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed for use in systems that require moderate load power such as LEDs. Integrated voltage clamps in the outputs provide protection against inductive transients making the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +125 °C • Low RDSon • Eight Power EDNMOS transistor outputs of 100 mA continuous current • 250 mA current limit capability • Output clamping voltage 33 V • 30 mJ avalanche energy capability • Enhanced cascading for multiple stages • All registers cleared with single input • Low power consumption • ESD protection: • HBM AEC-Q100-002 revision D exceeds 2500 V • CDM AEC-Q100-011 revision B exceeds 1000 V • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Applications • LED sign • Graphic status panel • Fault status indicator Nexperia NPIC6C596-Q100 Power logic 8-bit shift register; open-drain outputs 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version NPIC6C596D-Q100 -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 NPIC6C596PW-Q100 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 NPIC6C596BQ-Q100 -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal SOT763-1 enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 5. Functional diagram 15 SHCP 2 DS MR 7 Fig. 1. Logic symbol 10 STCP Q0 3 Q1 4 Q2 5 Q3 6 Q4 11 Q5 12 Q6 13 Q7 14 Q7S 9 OE 8 aaa-002547 VCC 2 DS 15 SHCP 7 MR 8-STAGE SHIFT REGISTER Q7S 9 10 STCP 8-BIT STORAGE REGISTER 8 OE OPEN-DRAIN OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Fig. 2. 345 6 Functional diagram 11 12 13 14 aaa-002548 Qn 33 V GND Fig. 3. Schematic of all inputs aaa-002550 Fig. 4. GND aaa-002551 Schematic of open-drain outputs (Qn) NPIC6C596_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 June 2020 © Nexperia B.V. 2020. All rights reserved 2 / 18 Nexperia DS SHCP MR STCP OE STAGE 0 DQ FF0 CP R NPIC6C596-Q100 Power logic 8-bit shift register; open-drain outputs STAGE 1 TO 6 D Q STAGE 7 DQ FF7 CP R STAGE 7S DQ FF7 CP R Q7S R DQ FF CP R DQ FF CP GND GND Fig. 5. Logic diagram SHCP OE DS STCP MR Q1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 76543210 Fig. 6. Timing diagram aaa-002552 Q7 5V GND 5V GND 5V GND 5V GND 5V GND VOH VOL aaa-002553 NPIC6C596_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 June 2020 © Nexperia B.V. 2020. All rights reserved 3 / 18 Nexperia 6. Pinning information NPIC6C596-Q100 Power logic 8-bit shift register; open-drain outputs 6.1. Pinning NPIC6C596-Q100 VCC 1 DS 2 Q0 3 Q1 4 Q2 5 Q3 6 MR 7 OE 8 16 GND 15 SHCP 14 Q7 13 Q6 12 Q5 11 Q4 10 STCP 9 Q7S aaa-002554 Fig. 7. Pin configuration SOT109-1 (SO16) and SOT403-1 (TSSOP16) 1 VCC 16 GND NPIC6C596-Q100 terminal 1 index area DS 2 Q0 3 Q1 4 Q2 5 Q3 6 MR 7 GND(1) 15 SHCP 14 Q7 13 Q6 12 Q5 11 Q4 10 STCP OE 8 Q7S 9 aaa-002555 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected t.


NPIC6C596A-Q100 NPIC6C596-Q100 NPIC6C595-Q100


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)