NPIC6C595-Q100 Datasheet (data sheet) PDF





NPIC6C595-Q100 Datasheet, Power logic 8-bit shift register

NPIC6C595-Q100   NPIC6C595-Q100  

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NPIC6C595-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 1 12 July 2012 Product data sheet 1. General description The NPIC6C595-Q100 is an 8-bit serial-in/serial or paralle l-out shift register with a storage reg ister and open-drain outputs. Both the shift and storage register have separat e clocks. The device features a serial input (DS) and a serial output

NPIC6C595-Q100 Datasheet, Power logic 8-bit shift register

NPIC6C595-Q100   NPIC6C595-Q100  
(Q7S) to enable cascading and an asynch ronous reset input (MR). A LOW on MR re sets both the shift register and storag e register. Data is shifted on the LOW- to-HIGH transitions of the SHCP input. The data in the shift register is trans ferred to the storage register on a LOW -to-HIGH transition of the STCP input a nd to the Q7S output on a LOW-to-HIGH t ransition of the SHCP input.








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