MPC8569E

Freescale Semiconductor Data Sheet: Technical Data MPC8569E PowerQUICC III Integrated Processor Hardware Specifications Document Number: MPC8569EEC Rev. 2, 10/2013 MPC8569E High-performance, 32-bit e500 core, scaling up to 1.33 GHz, that implements the Power Architecture® technology – 2799 MIPS at 1.33 GHz (estimated Dhrystone 2.1) – 36-bit physical addressing – Double-precision embedded floating point APU using 64-bit operands – Embedded vector and scalar single-precision floating-point APUs using 32- or 64-bit operands – Memory management unit (MMU) Integrated L1/L2 cache – L1 cache—32-Kbyte data and 32-Kbyte instruction – L2 cache—512-Kbyte (8-way set associative) Two DDR2/DDR3 SDRAM memory controllers with full ECC support – One 64-bit or two 32-bit data bus configuration – Up to 400 MHz clock (800 MHz data rate) – Supporting up to 16 Gbytes of main memory – Using ECC, detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble – Invoke a level of system power management by asserting MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode – Both hardware and software options to support battery-backed main memory – Initialization bypass feature that allow system designers to prevent re-initialization of main memory during system power on following abnormal shutdown Integrated security engine (SEC) optimized to process all the algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, IEEE Std 80...