MCUs. SAME51N20 Datasheet

SAME51N20 Datasheet PDF


Part

SAME51N20

Description

32-bit ARM Cortex-M4F MCUs

Manufacture

Microchip

Page 30 Pages
Datasheet
Download SAME51N20 Datasheet


SAME51N20 Datasheet
SAM D5x/E5x Family Data
Sheet
32-bit ARM® Cortex®-M4F MCUs with 1 Msps 12-bit ADC,
QSPI, USB, Ethernet, and PTC
Features
Operating Conditions:
• 1.71V to 3.63V, -40°C to +125°C, DC to 100 MHz
• 1.71V to 3.63V, -40°C to +105°C, DC to 120 MHz
• 1.71V to 3.63V, -40°C to +85°C, DC to 120 MHz
Core: 120 MHz ARM® Cortex®-M4
• 403 CoreMark® at 120 MHz
• 4 KB combined instruction cache and data cache
• 8-zones Memory Protection Unit (MPU)
• Thumb®-2 instruction set
• Embedded Trace Module (ETM) with instruction trace stream
• Core Sight Embedded Trace Buffer (ETB)
• Trace Port Interface Unit (TPIU)
• Floating Point Unit (FPU)
Memories
• 1 MB/512 KB/256 KB in-system self-programmable Flash with:
– Error Correction Code (ECC)
– Dual bank with Read-While-Write (RWW) support
– EEPROM hardware emulation
• 256/192/128 KB SRAM Main Memory
– 128/96/64 KB of Error Correction Code (ECC) RAM option
• Up to 4 KB of Tightly Coupled Memory (TCM)
• Up to 8 KB additional SRAM
– Can be retained in backup mode
• Eight 32-bit backup registers
System
• Power-on Reset (POR) and Brown-out detection (BOD)
• Internal and external clock options
• External Interrupt Controller (EIC)
• 16 external interrupts
• One non-maskable interrupt
• Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
© 2018 Microchip Technology Inc.
Datasheet
DS60001507C-page 1

SAME51N20 Datasheet
SAM D5x/E5x Family Data Sheet
Power Supply
• Idle, Standby, Hibernate, Backup, and Off sleep modes
• SleepWalking peripherals
• Battery backup support
• Embedded Buck/LDO regulator supporting on-the-fly selection
High-Performance Peripherals
• 32-channel Direct Memory Access Controller (DMAC)
– Built-in CRC, with memory CRC generation/monitor hardware support
• Up to two SD(HC) Memory Card Interfaces (SDHC)
– Up to 50 MHz operation
– 4-bit or 1-bit interface
– Compatibility with SD and SDHC memory card specification version 3.01
– Compatibility with SDIO specification version 3.0
– Compliant with JDEC specification, MMC memory cards V4.51
• One Quad I/O Serial Peripheral Interface (QSPI)
– eXecute-In-Place (XIP) support
– Dedicated AHB memory zone
• One Ethernet MAC (SAM E53 and SAM E54)
– 10/100 Mbps in MII and RMII with dedicated DMA
– IEEE 1588 Precision Time Protocol (PTP) support
– IEEE 1588 Time Stamping Unit (TSU) support
– IEEE802.3AZ energy efficiency support
– Support for 802.1AS and 1588 precision clock synchronization protocol
– Wake on LAN support
• Up to two Controller Area Network CAN (SAM E51 and SAM E54)
– Support for CAN2.0 A/B and CAN-FD (ISO 11898-1:2015)
• One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
– Embedded host and device function
– Eight endpoints
– On-chip transceiver with integrated serial resistor
System Peripherals
• 32-channel Event System
• Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as either:
– USART with full-duplex and single-wire half-duplex configuration
– ISO7816
– I2C up to 3.4MHz
– SPI
– LIN master/slave
– RS485
– SPI inter-byte space
• Up to eight 16-bit Timers/Counters (TC) each configurable as:
– 16-bit TC with two compare/capture channels
– 8-bit TC with two compare/capture channels
© 2018 Microchip Technology Inc.
Datasheet
DS60001507C-page 2


Features Datasheet pdf SAM D5x/E5x Family Data Sheet 32-bit ARM ® Cortex®-M4F MCUs with 1 Msps 12-bit ADC, QSPI, USB, Ethernet, and PTC Feat ures Operating Conditions: • 1.71V to 3.63V, -40°C to +125°C, DC to 100 MH z • 1.71V to 3.63V, -40°C to +105°C , DC to 120 MHz • 1.71V to 3.63V, -40 °C to +85°C, DC to 120 MHz Core: 120 MHz ARM® Cortex®-M4 • 403 CoreMark at 120 MHz • 4 KB combined instruct ion cache and data cache • 8-zones Me mory Protection Unit (MPU) • Thumb®- 2 instruction set • Embedded Trace Mo dule (ETM) with instruction trace strea m • Core Sight Embedded Trace Buffer (ETB) • Trace Port Interface Unit (TP IU) • Floating Point Unit (FPU) Memor ies • 1 MB/512 KB/256 KB in-system se lf-programmable Flash with: – Error C orrection Code (ECC) – Dual bank with Read-While-Write (RWW) support – EEP ROM hardware emulation • 256/192/128 KB SRAM Main Memory – 128/96/64 KB of Error Correction Code (ECC) RAM option • Up to 4 KB of Tightly Coupled Memory (TCM) • Up to 8 KB additional SRAM – Can be retained in backup mode •.
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