Document
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 5 — 27 August 2021
Product data sheet
1. General description
The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
• Wide supply voltage range from 1.2 V to 3.6 V • Overvoltage tolerant inputs to 5.5 V • CMOS low power dissipation • Direct interface with TTL levels • IOFF circuitry provides partial Power-down mode operation • 8-bit positive edge-triggered register • Independent register and 3-state buffer operation • Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
3. Ordering information
Table 1. Ordering information Type number Package
Temperature range Name
Description
74LVC374AD -40 °C to +125 °C SO20
plastic small outline package; 20 leads; body width 7.5 mm
74LVC374APW -40 °C to +125 °C
TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm
74LVC374ABQ -40 °C to +125 °C
DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm
Version SOT163-1
SOT360-1
SOT764-1
4. Functional diagram
11
CP
3 D0
Q0 2
4 D1
Q1 5
7 D2
Q2 6
8 D3
Q3 9
13 D4
Q4 12
14 D5
Q5 15
17 D6
Q6 16
18 D7
Q7 19
OE
1 mna891
Fig. 1. Logic symbol
1
EN
11
C1
3 1D 4 7 8 13 14 17 18
Fig. 2. IEC logic symbol
2 5 6 9 12 15 16 19
mna196
Fig. 3. Functional diagram
3 D0
4 D1
7 D2
8 D3
FF1
13 D4
to FF8
14 D5
17 D6
18 D7
11 CP 1 OE
3-STATE OUTPUTS
Q0 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19
mna892
74LVC374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 August 2021
© Nexperia B.V. 2021. All rights reserved
2 / 15
Nexperia
D0
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
D1
D2
D3
D4
D5
D6
D7
DQ CP
FF1
DQ CP
FF2
DQ CP
FF3
DQ CP
FF4
DQ CP
FF5
DQ CP
FF6
DQ CP
FF7
DQ CP
FF8
CP OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig. 4. Logic diagram
5. Pinning information
5.1. Pinning
74LVC374A
OE 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10
20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP
001aad040
Fig. 5. Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20)
1 OE 20 VCC
terminal 1 index area
74LVC374A
Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9
GND(1)
19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4
GND 10 CP 11
001aad088
Fig. 6.
Transparent top view
(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND.
Pin configuration SOT764-1 (DHVQFN20)
74LVC374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 August 2021
© Nexperia B.V. 2021. All rights reserved
3 / 15
Nexperia
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
5.2. Pin description
Table 2. Pin description Symbol OE Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 D0, D1, D2, D3, D4, D5, D6, D7 GND CP VCC
Pin 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20
Description output enable input (active LOW) 3-state flip-flop output data input ground (0 V) clock input (LOW-to-HIGH, edge-triggered) supply voltage
6. Functional description
Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition.
Operating mode
Input
Internal flip-flop Output
OE
CP
Dn
Qn
Load and read .