Document
74LVC244A-Q100;
74LVCH244A-Q100
Octal buffer/line driver; 3-state
Rev. 6 — 15 February 2021
Product data sheet
1. General description
The 74LVC244A-Q100; 74LVCH244A-Q100 is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V and 5 V environment.
The 74LVCH244A-Q100 bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 V to 3.6 V • CMOS low-power consumption • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • High-impedance when VCC = 0 V • Bus hold on all data inputs (74LVCH244A-Q100 only) • Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) • Multiple package options • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
Nexperia
74LVC244A-Q100; 74LVCH244A-Q100
Octal buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
74LVC244AD-Q100 74LVCH244AD-Q100
-40 °C to +125 °C
SO20
plastic small outline package; 20 leads; body width 7.5 mm
74LVC244APW-Q100 -40 °C to +125 °C 74LVCH244APW-Q100
TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm
74LVC244ABQ-Q100 -40 °C to +125 °C 74LVCH244ABQ-Q100
DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm
4. Functional diagram
Version SOT163-1
SOT360-1
SOT764-1
1 EN
2
18
4
16
6
14
8
12
19 EN
11
9
13
7
15
5
17
3
mna873
Fig. 1. IEC logic diagram
1A0 2
1A1 4
1A2 6 8 1A3
1OE 1
2A0 17 15 2A1
2A2 13
2A3 11 19 2OE
Fig. 2. Functional diagram
1Y0 18
1Y1 16
1Y2 14
1Y3 12
2Y0 3
2Y1 5
2Y2 7
2Y3 9
mna875
74LVC_LVCH244A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 15 February 2021
© Nexperia B.V. 2021. All rights reserved
2 / 15
Nexperia
Fig. 3. Logic symbol
2 1A0
4 1A1
6 1A2 1A3 8 1OE 1
5. Pinning information
74LVC244A-Q100; 74LVCH244A-Q100
Octal buffer/line driver; 3-state
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3 2A3 11 2OE 19
3 2Y0 5 2Y1 7
2Y2 9 2Y3
mna874
5.1. Pinning
74LVC244A 74LVCH244A
1OE 1 1A0 2 2Y0 3 1A1 4 2Y1 5 1A2 6 2Y2 7 1A3 8 2Y3 9 GND 10
20 VCC 19 2OE 18 1Y0 17 2A0 16 1Y1 15 2A1 14 1Y2 13 2A2 12 1Y3 11 2A3
001aad113
Fig. 4. Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20)
terminal 1 index area
74LVC244A 74LVCH244A
1 1OE 20 VCC
1A0 2 2Y0 3 1A1 4 2Y1 5 1A2 6 2Y2 7 1A3 8 2Y3 9
GND(1)
19 2OE 18 1Y0 17 2A0 16 1Y1 15 2A1 14 1Y2 13 2A2 12 1Y3
GND 10 2A3 11
001aad 114
Fig. 5.
Transparent top view
(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND.
Pin configuration SOT764-1 (DHVQFN20)
74LVC_LVCH244A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 15 February 2021
© Nexperia B.V. 2021. All rights reserved
3 / 15
Nexperia
74LVC244A-Q100; 74LVCH244A-Q100
Octal buffer/line driver; 3-state
5.2. Pin description
Table 2. Pin description Symbol 1OE, 2OE 1A0, 1A1, 1A2, 1A3 2Y0, 2Y1, 2Y2, 2Y3 GND 2A0, 2A1, 2A2, 2A3 1Y0, 1Y1, 1Y2, 1Y3, VCC
Pin 1, 19 2, 4, 6, 8 3, 5, 7, 9 10 17, 15, 13, 11 18, 16, 14, 12 20
Description output enable input (active low) data input data output ground (0 V) data input data output supply voltage
6. Functional description
Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Control
Input
Output
nOE
nAn
nYn
L
L
L
L
H
H
H
X
Z
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
.