Document
STM32F722xx STM32F723xx
Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 512KB Flash 256+16+4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
Datasheet - production data
Features
• Core: Arm® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator) and L1-cache: 8 Kbytes of data cache and 8 Kbytes of instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1) and DSP instructions.
• Memories – Up to 512 Kbytes of Flash memory with protection mechanisms (read and write protections, proprietary code readout protection (PCROP))
– 528 bytes of OTP memory
– SRAM: 256 Kbytes (including 64 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM (available in the lowest power modes)
– Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
• Dual mode Quad-SPI
• Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Dedicated USB power
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1% accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low-power – Sleep, Stop and Standby modes
LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm)
UFBGA144 (7 x 7 mm) WLCSP100 UFBGA176 (10 x 10 mm) (0.4 mm pitch)
LQFP176 (24 x 24 mm)
– VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes of backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWMs or pulse counter and quadrature (incremental) encoder inputs. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Debug mode – SWD and JTAG interfaces – Cortex®-M7 Trace Macrocell™
• Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 108 MHz
– Up to 138 5 V-tolerant I/Os
• Up to 21 communication interfaces – Up to 3× I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)
– Up to 5 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2Ss for audio class accuracy via internal audio PLL or external clock
– 2 x SAIs (serial audio interface)
July 2022
This is information on a product in full production.
DS11853 Rev 9
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STM32F722xx STM32F723xx
– 1 x CAN (2.0B active)
– 2 x SDMMCs
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG controller with on-chip PHY
– USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and on-chip Hi-speed PHY or ULPI depending on the part number
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
• True random number generator
Table 1. Device summary
Reference
Part number
STM32F722xx STM32F723xx
STM32F722IC, STM32F722IE, STM32F722RC, STM32F722RE, STM32F722VC, STM32F722VE, STM32F722ZC, STM32F722ZE STM32F723IC, STM32F723IE, STM32F723VC, STM32F723VE, STM32F723ZC, STM32F723ZE
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DS11853 Rev 9
STM32F722xx STM32F723xx
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 STM32F723xx versus STM32F722xx LQFP100/ LQFP144/ LQFP176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Arm Cortex-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 23
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 Quad-SPI memory interface (QUADSPI) . . . .