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NCD5701A Dataheets PDF



Part Number NCD5701A
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description High Current IGBT Gate Drivers
Datasheet NCD5701A DatasheetNCD5701A Datasheet (PDF)

NCD5701A, NCD5701B, NCD5701C High Current IGBT Gate Drivers The NCD5701A, NCD5701B and NCD5701C are high−current, high−performance stand−alone IGBT drivers for high power applications that include solar inverters, motor control and uninterruptible power supplies. The devices offer a cost−effective solution by eliminating external output buffer. Devices protection features include accurate Under−voltage−lockout (UVLO), desaturation protection (DESAT) and Active Low FAULT output. The drivers also.

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NCD5701A, NCD5701B, NCD5701C High Current IGBT Gate Drivers The NCD5701A, NCD5701B and NCD5701C are high−current, high−performance stand−alone IGBT drivers for high power applications that include solar inverters, motor control and uninterruptible power supplies. The devices offer a cost−effective solution by eliminating external output buffer. Devices protection features include accurate Under−voltage−lockout (UVLO), desaturation protection (DESAT) and Active Low FAULT output. The drivers also feature an accurate 5.0 V output. The drivers are designed to accommodate a wide voltage range of bias supplies including unipolar and NCD5701B even bipolar voltages. Depending on the pin configuration the devices also include Active Miller Clamp (NCD5701A) and separate high and low (VOH and VOL) driver outputs for system design convenience (NCD5701C). All three available pin configuration variants have 8−pin SOIC package. Features • High Current Output (+4/−6 A) at IGBT Miller Plateau voltages • Low Output Impedance for Enhanced IGBT Driving • Short Propagation Delay with Accurate Matching • Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer for Isolated Drive, Logic Compatibility for Non−isolated Drive • DESAT Protection with Programmable Delay • Tight UVLO Thresholds for Bias Flexibility • Wide Bias Voltage Range • This Device is Pb−Free, Halogen−Free and RoHS Compliant NCD5701A Features • Active Miller Clamp to Prevent Spurious Gate Turn−on NCD5701B Features • Negative Output Voltage for Enhanced IGBT Driving NCD5701C Features • Separate Outputs for VOL and VOH Typical Applications • Solar Inverters • Motor Control • Uninterruptible Power Supplies (UPS) • Rapid Shutdown for Photovoltaic Systems www.onsemi.com 8 1 SOIC−8 D SUFFIX CASE 751 MARKING DIAGRAM 8 NCD5701X ALYW G 1 NCD5701 = Specific Device Code X = A, B or C A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package PIN CONNECTIONS VIN VREF FLT DESAT 1 2 3 4 8 CLAMP 7 GND 6 VO 5 VCC NCD5701A VIN VREF FLT DESAT 1 2 3 4 8 VEE 7 GND 6 VO 5 VCC NCD5701B VIN VREF FLT DESAT 1 2 3 4 8 GND 7 VOL 6 VOH 5 VCC NCD5701C ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2017 June, 2017 − Rev. 4 1 Publication Order Number: NCD5701/D NCD5701A, NCD5701B, NCD5701C NCD5701A VREF DESAT VCC VO CLAMP VIN GND VCC FLT NCD5701B VREF DESAT VCC VO VIN GND VEE FLT VCC VEE NCD5701C VREF DESAT VCC VOH VOL VIN GND FLT VCC Figure 1. Simplified Application Schematics www.onsemi.com 2 NCD5701A, NCD5701B, NCD5701C FLT DESAT SET QS Q CLR R IDESAT-CHG VDESAT-THR + - VREF RIN-H VIN VREF VCC Bandgap VUVLO + TSD DELAY SET SQ R CLR Q NCD5701A VCC ÏDELAY SET SQ R CLR Q - + VMC-THR Ï GND Figure 2(a). Detailed Block Diagram NCD5701A NCD5701A VREF VIN CLAMP CLAMP VREF VCC LDO GND Logic Unit FLT DESAT TSD VCC UVLO DESAT VO VCC VO CLAMP Figure 2(b). Simplified Block Diagram NCD5701A www.onsemi.com 3 NCD5701A, NCD5701B, NCD5701C FLT DESAT SET QS Q CLR R IDESAT-CHG VDESAT-THR + - VREF RIN-H VIN VREF VCC Bandgap VUVLO + TSD DELAY SET SQ R CLR Q NCD5701B VCC ÏDELAY VEE VO GND Figure 3(a). Detailed Block Diagram NCD5701B VEE VREF VIN NCD5701B VEE VREF VCC LDO GND Logic Unit FLT DESAT TSD VCC UVLO DESAT VO VCC Figure 3(b). Simplified Block Diagram NCD5701B www.onsemi.com 4 NCD5701A, NCD5701B, NCD5701C FLT DESAT SET QS Q CLR R IDESAT-CHG VDESAT-THR + - VREF RIN-H VIN VREF VCC Bandgap VUVLO + TSD DELAY SET SQ R CLR Q NCD5701C VCC ÏDELAY VOH VOL GND Figure 4(a). Detailed Block Diagram NCD5701C NCD5701C VREF VIN GND VREF VCC LDO VOL Logic Unit FLT DESAT TSD VCC UVLO DESAT VOH VCC Figure 4(b). Simplified Block Diagram NCD5701C www.onsemi.com 5 NCD5701A, NCD5701B, NCD5701C Table 1. PIN FUNCTION DESCRIPTION Pin Name No. I/O/x Description VIN 1 I Input signal to control the output. In applications which require galvanic isolation, VIN is generated at the opto output, the pulse transformer secondary or the digital isolator output. There is a signal inversion from VIN to VO (VOH/VOL). VIN is internally clamped to 5.5 V and has a pull− up resistor of 1 MW to ensure that an output is low in the absence of an input signal. A minimum pulse−width is required at VIN before VO (VOH/VOL) is activated. VREF 2 O 5 V Reference generated within the driver is brought out to this pin for external bypassing and for powering low bias circuits (such as digital isolators). FLT 3 O Fault output (active low) that allows communication to the main controller that the driver has encountered a fault condition and has deactivated the output. Capable of driving optos or digital isolators when isolation is required. (Truth Table is provided in the datasheet to indicate conditions under which this signal is ass.


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