AND gate. 74AHCT2G08 Datasheet

74AHCT2G08 gate. Datasheet pdf. Equivalent


nexperia 74AHCT2G08
74AHC2G08; 74AHCT2G08
Dual 2-input AND gate
Rev. 6 — 21 March 2018
Product data sheet
1 General description
The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device.
The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates.
2 Features and benefits
Symmetrical output impedance
High noise immunity
ESD protection:
• – HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from -40 °C to +80 °C and from -40 °C to +125 °C
3 Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G08DP -40 °C to +125 °C TSSOP8
74AHCT2G08DP
74AHC2G08DC -40 °C to +125 °C VSSOP8
74AHCT2G08DC
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm


74AHCT2G08 Datasheet
Recommendation 74AHCT2G08 Datasheet
Part 74AHCT2G08
Description Dual 2-input AND gate
Feature 74AHCT2G08; 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 6 — 21 March 2018 Product data sheet 1 General d.
Manufacture nexperia
Datasheet
Download 74AHCT2G08 Datasheet




nexperia 74AHCT2G08
Nexperia
74AHC2G08; 74AHCT2G08
Dual 2-input AND gate
4 Marking
Table 2. Marking
Type number
74AHC2G08DP
74AHCT2G08DP
74AHC2G08DC
74AHCT2G08DC
Marking code[1]
A08
C08
A08
C08
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5 Functional diagram
1 1A
2 1B
5 2A
6 2B
Figure 1.  Logic symbol
1Y 7
2Y 3
mna724
1 &7
2
5 &3
6
mna725
Figure 2.  IEC logic symbol
A
B
Figure 3.  Logic diagram (one gate)
Y
mna221
74AHC_AHCT2G08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 21 March 2018
© Nexperia B.V. 2018. All rights reserved.
2 / 14



nexperia 74AHCT2G08
Nexperia
74AHC2G08; 74AHCT2G08
Dual 2-input AND gate
6 Pinning information
6.1 Pinning
74AHC2G08
74AHCT2G08
1A 1
1B 2
2Y 3
GND 4
8 VCC
7 1Y
6 2B
5 2A
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Figure 4.  Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
6.2 Pin description
Table 3. Pin description
Symbol
1A, 2A
1B, 2B
GND
1Y, 2Y
VCC
Pin
1, 5
2, 6
4
7, 3
8
7 Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
nA nB
LL
LH
HL
HH
Description
data input
data input
ground (0 V)
data output
supply voltage
Output
nY
L
L
L
H
74AHC_AHCT2G08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 21 March 2018
© Nexperia B.V. 2018. All rights reserved.
3 / 14





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