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74AHCT2G08 Dataheets PDF



Part Number 74AHCT2G08
Manufacturers nexperia
Logo nexperia
Description Dual 2-input AND gate
Datasheet 74AHCT2G08 Datasheet74AHCT2G08 Datasheet (PDF)

74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 6 — 21 March 2018 Product data sheet 1 General description The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device. The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates. 2 Features and benefits • Symmetrical output impedance • High noise immunity • ESD protection: • – HBM JESD22-A114E exceeds 2000 V – MM JESD22-A115-A exceeds 200 V – CDM JESD22-C101C exceeds 1000 V • Low power dissipation • Balanced propagation delays • Multiple pa.

  74AHCT2G08   74AHCT2G08



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74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 6 — 21 March 2018 Product data sheet 1 General description The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device. The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates. 2 Features and benefits • Symmetrical output impedance • High noise immunity • ESD protection: • – HBM JESD22-A114E exceeds 2000 V – MM JESD22-A115-A exceeds 200 V – CDM JESD22-C101C exceeds 1000 V • Low power dissipation • Balanced propagation delays • Multiple package options • Specified from -40 °C to +80 °C and from -40 °C to +125 °C 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC2G08DP -40 °C to +125 °C TSSOP8 74AHCT2G08DP 74AHC2G08DC -40 °C to +125 °C VSSOP8 74AHCT2G08DC Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm Nexperia 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate 4 Marking Table 2. Marking Type number 74AHC2G08DP 74AHCT2G08DP 74AHC2G08DC 74AHCT2G08DC Marking code[1] A08 C08 A08 C08 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5 Functional diagram 1 1A 2 1B 5 2A 6 2B Figure 1.  Logic symbol 1Y 7 2Y 3 mna724 1 &7 2 5 &3 6 mna725 Figure 2.  IEC logic symbol A B Figure 3.  Logic diagram (one gate) Y mna221 74AHC_AHCT2G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 21 March 2018 © Nexperia B.V. 2018. All rights reserved. 2 / 14 Nexperia 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate 6 Pinning information 6.1 Pinning 74AHC2G08 74AHCT2G08 1A 1 1B 2 2Y 3 GND 4 8 VCC 7 1Y 6 2B 5 2A 001aaj389 Figure 4.  Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2 Pin description Table 3. Pin description Symbol 1A, 2A 1B, 2B GND 1Y, 2Y VCC Pin 1, 5 2, 6 4 7, 3 8 7 Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Input nA nB LL LH HL HH Description data input data input ground (0 V) data output supply voltage Output nY L L L H 74AHC_AHCT2G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 21 March 2018 © Nexperia B.V. 2018. All rights reserved. 3 / 14 Nexperia 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate 8 Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC VI IIK IOK IO ICC IGND Tstg Ptot supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation VI < -0.5 V VO < -0.5 V or VO > VCC + 0.5 V -0.5 V < VO < VCC + 0.5 V Tamb = -40 °C to +125 °C -0.5 -0.5 [1] -20 [1] - -75 -65 [2] - +7.0 +7.0 ±20 ±25 75 +15.


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