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74AUP1G09 Dataheets PDF



Part Number 74AUP1G09
Manufacturers nexperia
Logo nexperia
Description Low-power 2-input AND gate
Datasheet 74AUP1G09 Datasheet74AUP1G09 Datasheet (PDF)

74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 7 — 14 January 2022 Product data sheet 1. General description The 74AUP1G09 is a single 2-input AND gate with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circu.

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74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 7 — 14 January 2022 Product data sheet 1. General description The 74AUP1G09 is a single 2-input AND gate with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • CMOS low power dissipation • High noise immunity • Overvoltage tolerant inputs to 3.6 V • Low static power consumption; ICC = 0.9 μA (maximum) • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Low noise overshoot and undershoot < 10 % of VCC • IOFF circuitry provides partial Power-down mode operation • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F Class 3A exceeds 5000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C Nexperia 74AUP1G09 Low-power 2-input AND gate with open-drain 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AUP1G09GW -40 °C to +125 °C Name TSSOP5 74AUP1G09GM -40 °C to +125 °C XSON6 74AUP1G09GN -40 °C to +125 °C XSON6 74AUP1G09GS -40 °C to +125 °C XSON6 74AUP1G09GX -40 °C to +125 °C X2SON5 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 × 0.8 × 0.32 mm Version SOT353-1 SOT886 SOT1115 SOT1202 SOT1226-3 4. Marking Table 2. Marking Type number 74AUP1G09GW 74AUP1G09GM 74AUP1G09GN 74AUP1G09GS 74AUP1G09GX Marking code [1] p9 p9 p9 p9 p9 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B1 A2 4Y 001aad598 Fig. 1. Logic symbol 1 & 4 2 001aad599 Fig. 2. IEC logic symbol Y A B Fig. 3. Logic diagram GND 001aad600 74AUP1G09 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2022 © Nexperia B.V. 2022. All rights reserved 2 / 17 Nexperia 6. Pinning information 6.1. Pinning 74AUP1G09 B1 A2 5 VCC GND 3 4Y 001aai728 Fig. 4. Pin configuration SOT353-1 (TSSOP5) 74AUP1G09 B1 A2 6.


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