Document
74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
Rev. 10 — 23 January 2023
Product data sheet
1. General description
The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
• Wide supply voltage range from 0.8 V to 3.6 V • CMOS low power dissipation • High noise immunity • Low static power consumption; ICC = 0.9 μA (maximum) • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Overvoltage tolerant inputs to 3.6 V • Low noise overshoot and undershoot < 10 % of VCC • IOFF circuitry provides partial Power-down mode operation • Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F Class 3A exceeds 5000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Applications
• Wave and pulse shaper • Astable multivibrator • Monostable multivibrator
Nexperia
74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
4. Ordering information
Table 1. Ordering information Type number Package
Temperature range 74AUP2G132DC -40 °C to +125 °C
74AUP2G132GT -40 °C to +125 °C
74AUP2G132GF -40 °C to +125 °C
74AUP2G132GN -40 °C to +125 °C
74AUP2G132GS -40 °C to +125 °C
74AUP2G132GX -40 °C to +125 °C
Name VSSOP8 XSON8 XSON8 XSON8 XSON8 X2SON8
Description
plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm
extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm
extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm
plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 1.35 × 0.8 × 0.32 mm
Version SOT765-1 SOT833-1 SOT1089 SOT1116 SOT1203 SOT1233-2
5. Marking
Table 2. Marking codes Type number 74AUP2G132DC 74AUP2G132GT 74AUP2G132GF 74AUP2G132GN 74AUP2G132GS 74AUP2G132GX
Marking code[1] aE2 aE2 aE aE aE aE
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
1A 1Y
1B
2A 2Y
2B 001aah880
Fig. 1. Logic symbol
&
& 001aah881
Fig. 2. IEC logic symbol
A Y
B 001aac532
Fig. 3. Logic diagram (one gate)
74AUP2G132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 23 January 2023
© Nexperia B.V. 2023. All rights reserve.