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74AUP1G08-Q100 Dataheets PDF



Part Number 74AUP1G08-Q100
Manufacturers nexperia
Logo nexperia
Description Low-power 2-input AND gate
Datasheet 74AUP1G08-Q100 Datasheet74AUP1G08-Q100 Datasheet (PDF)

74AUP1G08-Q100 Low-power 2-input AND gate Rev. 4 — 13 January 2022 Product data sheet 1. General description The 74AUP1G08-Q100 is a single 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preve.

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74AUP1G08-Q100 Low-power 2-input AND gate Rev. 4 — 13 January 2022 Product data sheet 1. General description The 74AUP1G08-Q100 is a single 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide supply voltage range from 0.8 V to 3.6 V • High noise immunity • CMOS low power dissipation • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • ESD protection: • MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V • HBM JESD22-A114F Class 3A. Exceeds 5000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) • Low static power consumption; ICC = 0.9 μA (maximum) • Low noise overshoot and undershoot < 10 % of VCC • Latch-up performance exceeds 100 mA per JESD 78 Class II • Overvoltage tolerant inputs to 3.6 V • Low noise overshoot and undershoot < 10 % of VCC • IOFF circuitry provides partial Power-down mode operation 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AUP1G08GW-Q100 -40 °C to +125 °C Name TSSOP5 74AUP1G08GM-Q100 -40 °C to +125 °C XSON6 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm Version SOT353-1 SOT886 Nexperia 74AUP1G08-Q100 Low-power 2-input AND gate 4. Marking Table 2. Marking Type number 74AUP1G08GW-Q100 74AUP1G08GM-Q100 Marking code[1] pE pE [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1B 2A Y4 mna113 Fig. 1. Logic symbol 1 & 4 2 mna114 Fig. 2. IEC logic symbol A B Fig. 3. Logic diagram Y mna221 6. Pinning information 6.1. Pinning 74AUP1G08 B1 A2 5 VCC GND 3 4Y 001aaf025 Fig. 4. Pin configuration SOT353-1 (TSSOP5) 74AUP1G08 B1 6 VCC A2 5 n.c. GND 3 4Y 001aaf026 Transparent top view Fig. 5. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol B A GND Y n.c. VCC Pin TSSOP5 1 2 3 4 5 XSON6 1 2 3 4 5 6 Description data input data input ground (0 V) data output not connected supply voltage 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 13 January 2022 © Nexperia B.V. 2022. All rights reserved 2 / 14 Nexperia 74AUP1G08-Q100 Low-power 2-input AND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Input A B L L L H H L H H Output Y L L L H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC IIK VI IOK VO IO ICC IGND Tstg Ptot supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation VI < 0 V VO < 0 V Active mode and Power-down mode VO = 0 V to VCC Tamb = -40 °C to +125 °C -0.5 -50 [1] -0.5 -50 [1] -0.5 - - -50 -65 [2] - +4.6 V - mA +4.6 V - mA +4.6 V ±20 mA +50 mA - mA +150 °C 250 mW [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb Δt/ΔV ambient temperature input transition rise and fall rate Conditions Active mode Power-down mode; VCC = 0 V VCC = 0.8 V to 3.6 V Min Max Unit 0.8 3.6 V 0 3.6 V 0 VCC V 0 3.6 V -40 +125 °C 0 200 ns/V 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 13 January 2022 © Nexperia B.V. 2022. All rights reserved 3 / 14 Nexperia 74AUP1G08-Q100 Low-power 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operat.


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